i2c.vhd

本源码是I2C接口VHDL的一个基本设计方案

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.std_logic_arith.all;
USE WORK.ROM.ALL;
ENTITY I2C IS
   PORT (       CLK           :IN   STD_LOGIC;            
                RST           :IN   STD_LOGIC;
                SDA_IN        :IN   STD_LOGIC;
                CHIP_RST      :OUT  STD_LOGIC;
                SCL           :OUT  STD_LOGIC;
                ENA_SDA_OUT   :OUT  STD_LOGIC;   
                SDA_OUT       :OUT  STD_LOGIC);
                
 END I2C;

ARCHITECTURE RTL OF I2C IS
TYPE STATE_TYPE IS (I2C_START,I2C_START_SDA_RST,I2C_START_SCL_RST,I2C_SLAVE_W,I2C_SUBADD,
        I2C_SUBADD_DATA,I2C_STOP,I2C_STOP_SCL_ST,I2C_NEXT_REG,I2C_END,RESET_CHIP,STATE_END,I2C_R,I2C_R_R,I2C_R_DATA);
TYPE SLAVE_W_STATE_TYPE IS ( SLAVE_W_7,SLAVE_W_SCL_ST,SLAVE_W_SCL_RST,SLAVE_W_SDA_RST,SLAVE_W_ACK,
        SLAVE_W_ACK_SCL_ST,SLAVE_W_ACK_H,SLAVE_W_ACK_SDA_O);
TYPE SUBADD_W_STATE_TYPE IS ( SUBADD_W_7,SUBADD_W_SCL_ST,SUBADD_W_SCL_RST,SUBADD_W_SDA_RST,SUBADD_W_ACK,
        SUBADD_W_ACK_SCL_ST,SUBADD_W_ACK_H,SUBADD_W_ACK_SDA_O);
TYPE SLAVE_R_STATE_TYPE IS (SLAVE_R_SCL_ST,SLAVE_R_SDA,SLAVE_R_SCL_RST,SLAVE_R_END,SLAVE_R_END_ACKM,
        SLAVE_R_END_ACKM_SCL_ST,SLAVE_R_END_ACKM_SDA_RST,SLAVE_R_END_ACKM_SCL_RST);

SIGNAL STATE           :STATE_TYPE;
SIGNAL SLAVE_W_STATE   :SLAVE_W_STATE_TYPE;
SIGNAL SUBADD_W_STATE  :SUBADD_W_STATE_TYPE;
SIGNAL SLAVE_R_STATE   :SLAVE_R_STATE_TYPE;    

SIGNAL SUBADD          : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL R_SUBADD        : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL TEST_SUBADD     : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL SUBADD_DATA     : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL SLAVE_W         : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL SLAVE_R         : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL SLAVE_R_DATA    : STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;
SIGNAL BIT_CNT         : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DELAY_CNT       : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ADD             : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL I2C_R_W_FLAG    : STD_LOGIC;
SIGNAL I2C_R_R_FLAG    : STD_LOGIC;
SIGNAL SLAVE_R_DATA_BIT     : STD_LOGIC;
SIGNAL SLAVE_R_DATA_FLAG    : STD_LOGIC;
SIGNAL REGISTER_NUMBER      : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL REG_NUM_PART         : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL REG_NUM_PART_FLAG    : STD_LOGIC_VECTOR(3 DOWNTO 0);--寄存器分成10个部分来初始化

BEGIN
PROCESS( CLK, RST )

BEGIN
   IF rising_edge(Clk) THEN
      IF (RST='0') THEN
         CHIP_RST<='1';
         SCL<='1';
         SDA_OUT<='1';
         ENA_SDA_OUT<='1';
		 SLAVE_W<="01000010"; --42H 
		 SLAVE_R<="01000011"; --43H
		 BIT_CNT<="0000";
         STATE<=I2C_START;
		 SLAVE_W_STATE<=SLAVE_W_7;
		 SUBADD_W_STATE<=SUBADD_W_7;
		 SLAVE_R_STATE<=SLAVE_R_SCL_ST;
		 SUBADD<="00000001";  --开始寄存器的地址
		 R_SUBADD<="00000001";--Read data from r_subadd
		 TEST_SUBADD<="01010101";
		 ADD<="0000000";
		 I2C_R_W_FLAG<='0';
		 I2C_R_R_FLAG<='0';
		 SLAVE_R_DATA_FLAG<='0';  
		 REGISTER_NUMBER<="0000000";
		 REG_NUM_PART<="0011001";	--19H=25 个寄存器
		 REG_NUM_PART_FLAG<="0000";
		 

      ELSE
	     
	    
         CASE STATE IS 
              WHEN  I2C_START=> 
              	                     SCL<='1';
                                     SDA_OUT<='1';
									 ENA_SDA_OUT<='1';
									 STATE<=I2C_START_SDA_RST;
			  WHEN  I2C_START_SDA_RST=>
			  	                     SDA_OUT<='0';
									 ENA_SDA_OUT<='1';
									 SCL<='1';
									 STATE<=I2C_START_SCL_RST;
			  WHEN  I2C_START_SCL_RST=>
			                         SDA_OUT<='0'; 
  									 SCL<='0';
									 STATE<=I2C_SLAVE_W;      -- 只有SCL是0时，SDA才可改变