divide_clk_test.vhd

本源码是I2C接口VHDL的一个基本设计方案

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIVIDE_CLK_TEST IS
   PORT (       CLK              :IN  STD_LOGIC; -- 33M的时钟或别的外部输入时钟
                DIVIDE_CLK       :OUT STD_LOGIC  -- 输出330K的时钟                       
         );
                
 END DIVIDE_CLK_TEST;

ARCHITECTURE RTL OF DIVIDE_CLK_TEST IS
SIGNAL  COUNTER: STD_LOGIC_VECTOR(9 DOWNTO 0):="0000000000";

BEGIN
 PROCESS(CLK)
 VARIABLE  DATA:     STD_LOGIC;
 BEGIN
    IF rising_edge(Clk) THEN
       IF(COUNTER="0011111100")THEN
          DATA:=NOT DATA;
          DIVIDE_CLK<= DATA;
          COUNTER<="0000000000"; 
       ELSE
          COUNTER<=COUNTER +'1';
       END IF;
    END IF;        
 END PROCESS;   
END RTL;