jiaotongdeng.tan.rpt

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                          ; To                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------+-----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~15            ; jiaotongdeng:inst|count_down[2]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~15            ; jiaotongdeng:inst|count_down[4]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~14            ; jiaotongdeng:inst|count_down[4]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~15            ; jiaotongdeng:inst|count_down[5]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~14            ; jiaotongdeng:inst|count_down[5]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~16            ; jiaotongdeng:inst|count_down[5]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~15            ; jiaotongdeng:inst|count_down[6]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~14            ; jiaotongdeng:inst|count_down[6]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; jiaotongdeng:inst|current_state~16            ; jiaotongdeng:inst|count_down[6]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; jiaotongdeng:inst|current_state~15            ; jiaotongdeng:inst|count_down[0]               ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; jiaotongdeng:inst|current_state~14            ; jiaotongdeng:inst|count_down[0]               ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; jiaotongdeng:inst|current_state~14            ; jiaotongdeng:inst|count_down[2]               ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 45.45 MHz ( period = 22.000 ns )                    ; jiaotongdeng:inst|current_state~16            ; jiaotongdeng:inst|count_down[4]               ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|temp                        ; jiaotongdeng:inst|count_down[2]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[2]               ; jiaotongdeng:inst|count_down[2]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[7]               ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[6]               ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|temp                        ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[2]               ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[1]               ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; jiaotongdeng:inst|count_down[0]               ; jiaotongdeng:inst|count_down[3]               ; CLK        ; CLK      ; None                        ; None                      ; 9.000 ns                ;