dingceng.map.rpt

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

+----------------------------+------------+------+---------------------+
; |jiaotongdeng              ; 52         ; 18   ; |jiaotongdeng       ;
+----------------------------+------------+------+---------------------+


+-------------------------------------------------------------------------------+
; State Machine - |jiaotongdeng|current_state                                   ;
+----------------------+------------------+------------------+------------------+
; Name                 ; current_state~16 ; current_state~15 ; current_state~14 ;
+----------------------+------------------+------------------+------------------+
; current_state.state0 ; 0                ; 0                ; 0                ;
; current_state.state6 ; 1                ; 1                ; 0                ;
; current_state.state5 ; 1                ; 0                ; 1                ;
; current_state.state4 ; 1                ; 0                ; 0                ;
; current_state.state3 ; 0                ; 1                ; 1                ;
; current_state.state2 ; 0                ; 1                ; 0                ;
; current_state.state1 ; 0                ; 0                ; 1                ;
; current_state.state7 ; 1                ; 1                ; 1                ;
+----------------------+------------------+------------------+------------------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |jiaotongdeng ;
+----------------+----------+--------------------------------------------------+
; Parameter Name ; Value    ; Type                                             ;
+----------------+----------+--------------------------------------------------+
; ared           ; 01010101 ; Binary                                           ;
; yerrow         ; 00000101 ; Binary                                           ;
; agreen         ; 01000000 ; Binary                                           ;
; aleft          ; 00010101 ; Binary                                           ;
; bred           ; 01100101 ; Binary                                           ;
; bgreen         ; 00110000 ; Binary                                           ;
; bleft          ; 00010101 ; Binary                                           ;
; state0         ; 00000000 ; Binary                                           ;
; state1         ; 00000001 ; Binary                                           ;
; state2         ; 00000010 ; Binary                                           ;
; state3         ; 00000011 ; Binary                                           ;
; state4         ; 00000100 ; Binary                                           ;
; state5         ; 00000101 ; Binary                                           ;
; state6         ; 00000110 ; Binary                                           ;
; state7         ; 00000111 ; Binary                                           ;
+----------------+----------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 26          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_bph ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/My_design/jiaotongdeng/dingceng.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed May 07 14:28:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dingceng -c dingceng
Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.v
    Info: Found entity 1: jiaotongdeng
Info: Found 1 design units, including 1 entities, in source file xianshi.v
    Info: Found entity 1: xianshi
Info: Found 1 design units, including 1 entities, in source file dingceng.bdf
    Info: Found entity 1: dingceng
Info: Elaborating entity "jiaotongdeng" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at jiaotongdeng.v(13): object "ared" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at jiaotongdeng.v(14): object "bred" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(19): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(23): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(52): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(57): truncated value with size 32 to match size of target (4)
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|jiaotongdeng|current_state" contains 8 states
Info: Selected Auto state machine encoding method for state machine "|jiaotongdeng|current_state"
Info: Encoding result for state machine "|jiaotongdeng|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "current_state~16"
        Info: Encoded state bit "current_state~15"
        Info: Encoded state bit "current_state~14"
    Info: State "|jiaotongdeng|current_state.state0" uses code string "000"
    Info: State "|jiaotongdeng|current_state.state6" uses code string "110"
    Info: State "|jiaotongdeng|current_state.state5" uses code string "101"
    Info: State "|jiaotongdeng|current_state.state4" uses code string "100"
    Info: State "|jiaotongdeng|current_state.state3" uses code string "011"
    Info: State "|jiaotongdeng|current_state.state2" uses code string "010"
    Info: State "|jiaotongdeng|current_state.state1" uses code string "001"
    Info: State "|jiaotongdeng|current_state.state7" uses code string "111"
Info: Ignored 26 buffer(s)
    Info: Ignored 26 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK" to global clock signal
    Info: Promoted clear signal driven by pin "EN" to global clear signal
Info: Implemented 70 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 52 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Wed May 07 14:28:09 2008
    Info: Elapsed time: 00:00:04