xianshi.v

来自「这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II」· Verilog 代码 · 共 46 行

module  xianshi(clk,temp_reg,seg,sl);
output[7:0]seg;
output[1:0]sl;
input clk;
input[7:0]temp_reg;
reg[7:0]seg_temp;
reg[1:0]sl_temp;
reg[3:0]disdata;
reg[12:0]count;
always@(posedge clk)
	begin
		count = count + 1;
	end
always@(count[12])
	begin
		case(count[12])
			1'b0:disdata <= temp_reg[3:0];
			1'b1:disdata <= temp_reg[7:4];
		endcase
	end
always@(count[12])
	begin
		case(count[12])
			1'b0:sl_temp <= 2'b01;
			1'b1:sl_temp <= 2'b10;
		endcase
	end	
always@(disdata)
	begin
		case(disdata)
			4'd0:seg_temp <= 8'hc0;
			4'd1:seg_temp <= 8'hf9;
			4'd2:seg_temp <= 8'ha4;
			4'd3:seg_temp <= 8'hb0;
			4'd4:seg_temp <= 8'h99;
			4'd5:seg_temp <= 8'h92;
			4'd6:seg_temp <= 8'h82;
			4'd7:seg_temp <= 8'hf8;
			4'd8:seg_temp <= 8'h80;
			4'd9:seg_temp <= 8'h90;
			default:seg_temp <= 8'hff;
		endcase
	end
	assign sl=sl_temp;
	assign seg=seg_temp;
endmodule