📄 jiaotongdeng.sim.vwf

📁 这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 100.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 100000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("CLK")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("LAMP")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("LAMP[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("LAMP[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LAMP";
}

SIGNAL("seg")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("seg[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("sl")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 2;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sl[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sl";
}

SIGNAL("sl[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "sl";
}

SIGNAL("ST")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

TRANSITION_LIST("CLK")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10000;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("LAMP[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 37721.0;
		LEVEL 1 FOR 32760.0;
		LEVEL 0 FOR 29519.0;
	}
}

TRANSITION_LIST("LAMP[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 21610.0;
		LEVEL 1 FOR 3640.0;
		LEVEL 0 FOR 8840.0;
		LEVEL 1 FOR 3640.0;
		LEVEL 0 FOR 54600.0;
		LEVEL 1 FOR 3640.0;
		LEVEL 0 FOR 4030.0;
	}
}

TRANSITION_LIST("LAMP[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 21610.0;
		LEVEL 0 FOR 48880.0;
		LEVEL 1 FOR 21840.0;
		LEVEL 0 FOR 7670.0;
	}
}

TRANSITION_LIST("LAMP[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 25250.0;
		LEVEL 1 FOR 8840.0;
		LEVEL 0 FOR 61880.0;
		LEVEL 1 FOR 4030.0;
	}
}

TRANSITION_LIST("LAMP[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 37730.0;
		LEVEL 0 FOR 32760.0;
		LEVEL 1 FOR 29510.0;
	}
}

TRANSITION_LIST("LAMP[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 54370.0;
		LEVEL 1 FOR 3640.0;
		LEVEL 0 FOR 8840.0;
		LEVEL 1 FOR 3640.0;
		LEVEL 0 FOR 29510.0;
	}
}

TRANSITION_LIST("LAMP[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 37730.0;
		LEVEL 1 FOR 16640.0;
		LEVEL 0 FOR 45630.0;
	}
}

TRANSITION_LIST("LAMP[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 58010.0;
		LEVEL 1 FOR 8840.0;
		LEVEL 0 FOR 33150.0;
	}
}

TRANSITION_LIST("seg[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 100000.0;
	}
}

TRANSITION_LIST("seg[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 801.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 1040.0;
			LEVEL 1 FOR 521.0;
			LEVEL 0 FOR 2599.0;
			LEVEL 1 FOR 1040.0;
		}
		LEVEL 0 FOR 1040.0;
		LEVEL 1 FOR 521.0;
		LEVEL 0 FOR 2599.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 2080.0;
		}
		LEVEL 1 FOR 1040.0;
		LEVEL 0 FOR 1040.0;
		LEVEL 1 FOR 521.0;
		LEVEL 0 FOR 2599.0;
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 2080.0;
		LEVEL 1 FOR 2080.0;
		LEVEL 0 FOR 1040.0;
		LEVEL 1 FOR 521.0;
		LEVEL 0 FOR 3639.0;
		LEVEL 1 FOR 27040.0;
		LEVEL 0 FOR 10920.0;
		LEVEL 1 FOR 11.0;
		LEVEL 0 FOR 1029.0;
		LEVEL 1 FOR 521.0;
		LEVEL 0 FOR 2599.0;
		LEVEL 1 FOR 1040.0;
		LEVEL 0 FOR 1040.0;
		LEVEL 1 FOR 521.0;
		LEVEL 0 FOR 2599.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 2080.0;
		}
		LEVEL 1 FOR 1040.0;
		LEVEL 0 FOR 399.0;
	}
}

TRANSITION_LIST("seg[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1841.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 520.0;
			LEVEL 0 FOR 1560.0;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 1560.0;
		}
		LEVEL 1 FOR 520.0;
		LEVEL 0 FOR 1560.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 2080.0;
		}
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 1560.0;
		LEVEL 1 FOR 520.0;
		LEVEL 0 FOR 1560.0;
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 2080.0;
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 2600.0;
		LEVEL 1 FOR 520.0;
		LEVEL 0 FOR 651.0;
		LEVEL 1 FOR 8189.0;
		LEVEL 0 FOR 9360.0;
		LEVEL 1 FOR 3120.0;
		LEVEL 0 FOR 9880.0;
		LEVEL 1 FOR 10411.0;
		LEVEL 0 FOR 1029.0;
		LEVEL 1 FOR 520.0;
		LEVEL 0 FOR 1560.0;
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 1560.0;
		LEVEL 1 FOR 520.0;
		LEVEL 0 FOR 1560.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 2080.0;
		}
		LEVEL 1 FOR 1560.0;
		LEVEL 0 FOR 919.0;
	}
}

TRANSITION_LIST("seg[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 801.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 520.0;
			LEVEL 0 FOR 520.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			NODE
			{
				REPEAT = 3;
				LEVEL 0 FOR 520.0;
				LEVEL 1 FOR 520.0;
			}
			LEVEL 0 FOR 520.0;
		}
		LEVEL 1 FOR 1560.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 520.0;
			LEVEL 1 FOR 520.0;
		}
		LEVEL 0 FOR 520.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1560.0;
			LEVEL 0 FOR 520.0;
			LEVEL 1 FOR 520.0;
			LEVEL 0 FOR 1040.0;
12 下一页
💿 文件大小 559 K
👤 上传用户 lwsnsfp17
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Verilog #Quartus #HDL #语言
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