jiaotongdeng.hier_info

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

|dingceng
LAMP[0] <= jiaotongdeng:inst.LAMP[0]
LAMP[1] <= jiaotongdeng:inst.LAMP[1]
LAMP[2] <= jiaotongdeng:inst.LAMP[2]
LAMP[3] <= jiaotongdeng:inst.LAMP[3]
LAMP[4] <= jiaotongdeng:inst.LAMP[4]
LAMP[5] <= jiaotongdeng:inst.LAMP[5]
LAMP[6] <= jiaotongdeng:inst.LAMP[6]
LAMP[7] <= jiaotongdeng:inst.LAMP[7]
CLK => jiaotongdeng:inst.CLK
CLK => xianshi:inst1.clk
ST => jiaotongdeng:inst.EN
seg[0] <= xianshi:inst1.seg[0]
seg[1] <= xianshi:inst1.seg[1]
seg[2] <= xianshi:inst1.seg[2]
seg[3] <= xianshi:inst1.seg[3]
seg[4] <= xianshi:inst1.seg[4]
seg[5] <= xianshi:inst1.seg[5]
seg[6] <= xianshi:inst1.seg[6]
seg[7] <= xianshi:inst1.seg[7]
sl[0] <= xianshi:inst1.sl[0]
sl[1] <= xianshi:inst1.sl[1]


|dingceng|jiaotongdeng:inst
CLK => count[24].CLK
CLK => count[23].CLK
CLK => count[22].CLK
CLK => count[21].CLK
CLK => count[20].CLK
CLK => count[19].CLK
CLK => count[18].CLK
CLK => count[17].CLK
CLK => count[16].CLK
CLK => count[15].CLK
CLK => count[14].CLK
CLK => count[13].CLK
CLK => count[12].CLK
CLK => count[11].CLK
CLK => count[10].CLK
CLK => count[9].CLK
CLK => count[8].CLK
CLK => count[7].CLK
CLK => count[6].CLK
CLK => count[5].CLK
CLK => count[4].CLK
CLK => count[3].CLK
CLK => count[2].CLK
CLK => count[1].CLK
CLK => count[0].CLK
CLK => CLK2.CLK
CLK => count[25].CLK
EN => always1~0.IN0
LAMP[0] <= LAMP~9.DB_MAX_OUTPUT_PORT_TYPE
LAMP[1] <= LAMP~8.DB_MAX_OUTPUT_PORT_TYPE
LAMP[2] <= LAMP~7.DB_MAX_OUTPUT_PORT_TYPE
LAMP[3] <= LAMP~5.DB_MAX_OUTPUT_PORT_TYPE
LAMP[4] <= LAMP~4.DB_MAX_OUTPUT_PORT_TYPE
LAMP[5] <= LAMP~3.DB_MAX_OUTPUT_PORT_TYPE
LAMP[6] <= LAMP~2.DB_MAX_OUTPUT_PORT_TYPE
LAMP[7] <= LAMP~0.DB_MAX_OUTPUT_PORT_TYPE
count_down[0] <= count_down[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[1] <= count_down[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[2] <= count_down[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[3] <= count_down[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[4] <= count_down[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[5] <= count_down[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[6] <= count_down[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count_down[7] <= count_down[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dingceng|xianshi:inst1
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[12].CLK
temp_reg[0] => disdata[0].DATAA
temp_reg[1] => disdata[1].DATAA
temp_reg[2] => disdata[2].DATAA
temp_reg[3] => disdata[3].DATAA
temp_reg[4] => disdata[0].DATAB
temp_reg[5] => disdata[1].DATAB
temp_reg[6] => disdata[2].DATAB
temp_reg[7] => disdata[3].DATAB
seg[0] <= seg_temp~6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= seg_temp~5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= seg_temp~4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= seg_temp~3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= seg_temp~2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= seg_temp~1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= seg_temp~0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <VCC>
sl[0] <= sl_temp~1.DB_MAX_OUTPUT_PORT_TYPE
sl[1] <= sl_temp~0.DB_MAX_OUTPUT_PORT_TYPE