dingceng.sim.qmsg

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 23 17:51:23 2008 " "Info: Processing started: Mon Jun 23 17:51:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off dingceng -c dingceng " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dingceng -c dingceng" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[7\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[7\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[7\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[6\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[6\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[6\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[5\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[5\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[5\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[4\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[4\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[4\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[3\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[3\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[2\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[2\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[2\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[1\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[1\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[1\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "seg\[0\] " "Warning: Compiler packed, optimized or synthesized away node \"seg\[0\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "seg\[0\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "sl\[1\] " "Warning: Compiler packed, optimized or synthesized away node \"sl\[1\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "sl\[1\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Warning" "WSIM_NO_OTERM_FOR_CHANNEL" "sl\[0\] " "Warning: Compiler packed, optimized or synthesized away node \"sl\[0\]\". Ignored vector source file node." {  } { { "F:/My_design/jiaotongdeng/dingceng.vwf" "" { Waveform "F:/My_design/jiaotongdeng/dingceng.vwf" "sl\[0\]" "0 ps" "0 ps" "" } }  } 0 0 "Compiler packed, optimized or synthesized away node \"%1!s!\". Ignored vector source file node." 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     47.76 % " "Info: Simulation coverage is      47.76 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "20247 " "Info: Number of transitions in simulation is 20247" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 10 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 23 17:51:28 2008 " "Info: Processing ended: Mon Jun 23 17:51:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}