dingceng.tan.qmsg

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LAMP\[7\] current_state~16 35.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"LAMP\[7\]\" through register \"current_state~16\" is 35.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 21.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 27 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { CLK } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns CLK2 2 REG LC4 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 11; REG Node = 'CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { CLK CLK2 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns CLK1 3 REG LC112 5 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC112; Fanout = 5; REG Node = 'CLK1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "9.000 ns" { CLK2 CLK1 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns current_state~16 4 REG LC91 15 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC91; Fanout = 15; REG Node = 'current_state~16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { CLK1 current_state~16 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 80.95 % ) " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.05 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "21.000 ns" { CLK CLK2 CLK1 current_state~16 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.000 ns" { CLK CLK~out CLK2 CLK1 current_state~16 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state~16 1 REG LC91 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC91; Fanout = 15; REG Node = 'current_state~16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { current_state~16 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns current_state~186 2 COMB LC83 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC83; Fanout = 1; COMB Node = 'current_state~186'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "9.000 ns" { current_state~16 current_state~186 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns LAMP\[7\] 3 PIN PIN_54 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'LAMP\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "4.000 ns" { current_state~186 LAMP[7] } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 84.62 % ) " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "13.000 ns" { current_state~16 current_state~186 LAMP[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.000 ns" { current_state~16 current_state~186 LAMP[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "21.000 ns" { CLK CLK2 CLK1 current_state~16 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.000 ns" { CLK CLK~out CLK2 CLK1 current_state~16 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "13.000 ns" { current_state~16 current_state~186 LAMP[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.000 ns" { current_state~16 current_state~186 LAMP[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp EN CLK 6.000 ns register " "Info: th for register \"temp\" (data pin = \"EN\", clock pin = \"CLK\") is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 27 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { CLK } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns CLK2 2 REG LC4 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 11; REG Node = 'CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { CLK CLK2 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns temp 3 REG LC111 41 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC111; Fanout = 41; REG Node = 'temp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { CLK2 temp } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 temp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 temp } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns EN 1 PIN PIN_1 46 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 46; PIN Node = 'EN'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { EN } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns temp 2 REG LC111 41 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC111; Fanout = 41; REG Node = 'temp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "7.000 ns" { EN temp } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "10.000 ns" { EN temp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { EN EN~out temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 temp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 temp } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "10.000 ns" { EN temp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { EN EN~out temp } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 14:28:16 2008 " "Info: Processing ended: Wed May 07 14:28:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}