dingceng.tan.qmsg

这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK1 " "Info: Detected ripple clock \"CLK1\" as buffer" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK2 " "Info: Detected ripple clock \"CLK2\" as buffer" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register current_state~15 register count_down\[5\]~reg0 43.48 MHz 23.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 43.48 MHz between source register \"current_state~15\" and destination register \"count_down\[5\]~reg0\" (period= 23.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state~15 1 REG LC102 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC102; Fanout = 15; REG Node = 'current_state~15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { current_state~15 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns count_down\[5\]~479 2 COMB LC103 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC103; Fanout = 1; COMB Node = 'count_down\[5\]~479'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { current_state~15 count_down[5]~479 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns count_down\[5\]~reg0 3 REG LC104 15 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC104; Fanout = 15; REG Node = 'count_down\[5\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { count_down[5]~479 count_down[5]~reg0 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns ( 77.78 % ) " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 22.22 % ) " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "9.000 ns" { current_state~15 count_down[5]~479 count_down[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.000 ns" { current_state~15 count_down[5]~479 count_down[5]~reg0 } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.000 ns - Smallest " "Info: - Smallest clock skew is -9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 27 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { CLK } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns CLK2 2 REG LC4 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 11; REG Node = 'CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { CLK CLK2 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns count_down\[5\]~reg0 3 REG LC104 15 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC104; Fanout = 15; REG Node = 'count_down\[5\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { CLK2 count_down[5]~reg0 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 count_down[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 count_down[5]~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 21.000 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 27 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { CLK } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns CLK2 2 REG LC4 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 11; REG Node = 'CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { CLK CLK2 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns CLK1 3 REG LC112 5 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC112; Fanout = 5; REG Node = 'CLK1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "9.000 ns" { CLK2 CLK1 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns current_state~15 4 REG LC102 15 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC102; Fanout = 15; REG Node = 'current_state~15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { CLK1 current_state~15 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 80.95 % ) " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.05 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "21.000 ns" { CLK CLK2 CLK1 current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.000 ns" { CLK CLK~out CLK2 CLK1 current_state~15 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 count_down[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 count_down[5]~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "21.000 ns" { CLK CLK2 CLK1 current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.000 ns" { CLK CLK~out CLK2 CLK1 current_state~15 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "9.000 ns" { current_state~15 count_down[5]~479 count_down[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.000 ns" { current_state~15 count_down[5]~479 count_down[5]~reg0 } { 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 count_down[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 count_down[5]~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "21.000 ns" { CLK CLK2 CLK1 current_state~15 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "21.000 ns" { CLK CLK~out CLK2 CLK1 current_state~15 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count_down\[6\]~reg0 EN CLK 3.000 ns register " "Info: tsu for register \"count_down\[6\]~reg0\" (data pin = \"EN\", clock pin = \"CLK\") is 3.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns EN 1 PIN PIN_1 46 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 46; PIN Node = 'EN'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { EN } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns count_down\[6\]~483 2 COMB LC100 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'count_down\[6\]~483'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "7.000 ns" { EN count_down[6]~483 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns count_down\[6\]~reg0 3 REG LC101 14 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC101; Fanout = 14; REG Node = 'count_down\[6\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { count_down[6]~483 count_down[6]~reg0 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 90.91 % ) " "Info: Total cell delay = 10.000 ns ( 90.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 9.09 % ) " "Info: Total interconnect delay = 1.000 ns ( 9.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "11.000 ns" { EN count_down[6]~483 count_down[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { EN EN~out count_down[6]~483 count_down[6]~reg0 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 6.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.000 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 27 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "" { CLK } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns CLK2 2 REG LC4 11 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 11; REG Node = 'CLK2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "1.000 ns" { CLK CLK2 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns count_down\[6\]~reg0 3 REG LC101 14 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC101; Fanout = 14; REG Node = 'count_down\[6\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "8.000 ns" { CLK2 count_down[6]~reg0 } "NODE_NAME" } "" } } { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 count_down[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 count_down[6]~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "11.000 ns" { EN count_down[6]~483 count_down[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { EN EN~out count_down[6]~483 count_down[6]~reg0 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 6.000ns 1.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dingceng" "UNKNOWN" "V1" "F:/My_design/jiaotongdeng/db/dingceng.quartus_db" { Floorplan "F:/My_design/jiaotongdeng/" "" "12.000 ns" { CLK CLK2 count_down[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out CLK2 count_down[6]~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}