h263_vld_n.sa

h263,jpeg,mpeg2编解码核心程序(TI DSP C64xx)

*          implicit offset of 60 and hence this code's length is actually   *
*          stored at location 65. The 65 th entry from the length table is  *
*          8 and corresponds to the length of the code.                     *
*                                                                           *
*                                                                           *
*          The entries in the Zig-Zag table are expected to be in the range *
*          0 .. 63, with no repeated entries.  The VLD starts reading the   *
*          Zig-Zag table at zz[1], and under normal circumstances will not  *
*          read past element zz[63].  However, when an invalid bitstream is *
*          encountered, elements as high as zz[126] may be accessed.  See   *
*          the MEMORY NOTE below for more information.                      *
*                                                                           *
*   ASSUMPTIONS                                                             *
*      Speculative reads are OK.  See MEMORY NOTE below.                    *
*                                                                           *
*      Short (as in, invalid due to truncation) bitstreams are followed     *
*      by sentinel values to halt VLD with an error condition, to prevent   *
*      underflow.                                                           *
*                                                                           *
*   MEMORY NOTE                                                             *
*      The VLD routine will read up to two full words beyond the final      *
*      position of the bitstream word pointer, as part of its lookahead.    *
*      The user must ensure that two words of valid memory exist there.     *
*                                                                           *
*      Speculative reads are performed to each of the following arrays:     *
*      (Ranges are in bytes, and are inclusive.)                            *
*                                                                           *
*          Table/Array            Valid Range   Accessed Range              *
*                                                                           *
*          Zig-Zag Table            0..63           0.  27                  *
*          Length Table             0..91           0..511                  *
*          Coef/Run Table           0..607          0..607                  *
*                                                                           *
*      The user should ensure that valid (eg. CPU readable) memory          *
*      exists in the required ranges past the end of each table.            *
*                                                                           *
*      Alternately, to ensure that these reads do not reduce cache          *
*      effectiveness (C6211) and do not access invalid memory, the          *
*      following table layout is recommended, as it causes all              *
*      speculative reads to land inside other valid table entries:          *
*                                                                           *
*          Bytes   0 .. 63    'zz'    Zig-Zag table                         *
*          Bytes  64 .. 159   'len'   Huffman-code Length table             *
*          Bytes 160 .. 767   'tab'   Huffman-code Coefficient/Run Table    *
*                                                                           *
*  NOTES                                                                    *
*      The input bitstream must be "word order", meaning that it is         *
*      accessed with word-wide reads.                                       *
*                                                                           *
*===========================================================================*
*      Copyright (C) 1997-1999 Texas Instruments Incorporated.              *
*                      All Rights Reserved                                  *
*===========================================================================*

            .global _h263_vld_nsa

_h263_vld_nsa: .cproc  A_bufPtr, B_bitPtr, A_tab, B_len, A_Q, B_dq, A_zz, B_idct, A_inter
            .no_mdep
            .reg  B_bit, A_len, B_len_, B_w1, B_vld_buf, B_t_w1
            .reg  B_w1_, A_vld_buf, B_f5, B_f7, B_nc1, B_esc
            .reg  A_nbit, B_nbit
            .reg  A_last, A_run, A_s, B_idx, A_idx
            .reg  B_buf, B_tab_, B_w0, A_EOB
            .reg  B_sl, B_w0_, B_c4, B_n5
            .reg  A_c63, B_c32, A_tmp
            .reg  B_nesc, A_bit25, A_bit15
            .reg  A_idx_
            .reg  A_lrl, B_lrl
            .reg  A_l_tmp, A_s_tmp
            .reg  A_err, A_err1, A_err2
            .reg  A_level, A_levelQ, B_levelQ
            .reg  A_zz_end, B_dq_s

            LDW         *A_bufPtr,   B_buf                ; buffer pointer
            LDW         *B_bitPtr,   B_bit                ; bit pointer
                                     
            MV          A_tab,       B_tab_               ; table pointer
            MV          B_len,       B_len_               ; length pointer
            MV          B_len_,      A_len                ; A side
                                     
            ADDK        352,         B_tab_               ; dcttab[176]
            ADDK        60,          B_len_               ; dctlen[60]
                                     
            MV          A_zz,        A_zz_end             ; End of zz array
            ADDK        63,          A_zz_end             ; zz_end = zz + 63
            SUB         A_zz,        A_inter,   A_zz      ; zz -= inter
                                     
            LDW         *+B_buf[0],             B_w0      ; w0 = buf[0]
            LDW         *+B_buf[1],             B_w1      ; w1 = buf[1]
                                                          
            ZERO        A_err2                            ; err     = 0
                                                          
            MVKL        32,         B_c32                 ; c32 = 32
            SUB         B_c32,      B_bit,      B_sl      ; sl  = 32 - bit
            SHL         B_w0,       B_sl,       B_w0_     ; w0_ = w0 << sl
            SHRU        B_w1,       B_bit,      B_w1_     ; w1_ = w1 >> bit
            OR          B_w0_,      B_w1_,      B_vld_buf ; w0_ + w1_
            SHL         B_c32,      9,          A_bit15
            SHL         A_bit15,    10,         A_bit25
                                                          
dectcoef_loop:                                            
            MV          B_vld_buf,              A_vld_buf ; vld_buf
            SHRU        B_vld_buf,  27,         B_f5      ; get first 5 bits
            SHRU        B_vld_buf,  23,         B_n5      ; get next5
            CMPLT       B_f5,       4,          B_c4      ; first5<4?
            SHRU        B_vld_buf,  25,         B_f7      ; get first 7 bits
            SUB         B_f7,       3,          B_nesc    ; is escape ?
                                                          
            LDBU        *+B_len_[B_f5],         B_nbit    ; if(c4)nbit=len_[f7]
  [ B_c4]   LDBU        *+B_len [B_n5],         B_nbit    ; nbit = len[f5]
                                                          
  [!B_nbit] MVK         2,          A_err2      
                                                          
            SHRU        A_vld_buf,  22,         A_idx_    ; idx_ is 10 bits
            SHRU        A_vld_buf,  20,         A_idx     ; idx  is 12 bits
  [ B_f5]   ADDAW       A_idx_,     16,         A_idx     ; if (f5) idx=idx_+64
                                                          
            LDH         *+A_tab [A_idx],        A_lrl     ; if(c4)lrl=tab_[idx]
            LDH         *+B_tab_[B_f7],         B_lrl     ; lrl = tab[f7]
  [!B_c4]   MV          B_lrl,      A_lrl                 ; Make copy
                                                          
            AND         A_vld_buf,  A_bit25,    A_last    ; ESCAPE last
            EXTU        A_vld_buf,  8,  26,     A_run     ; ESCAPE run
            EXT         A_vld_buf,  14, 24,     A_level   ; ESCAPE level
            CMPLT       A_level,    0,          A_s       ; A_s <- B_esc
                                                          
  [ B_nesc] AND         A_lrl,      A_bit15,    A_last    ; get last
  [ B_nesc] EXTU        A_lrl,      18, 25,     A_run     ; get run
            EXTU        A_lrl,      25, 25,     A_l_tmp   ; get level
            SUB         B_nbit,     1,          A_tmp     ; nrbits-1
            SHL         A_vld_buf,  A_tmp,      A_s_tmp   ; get sign A_s<-!B_esc
  [ B_nesc] CMPLT       A_s_tmp,    0,          A_s       ; get sign
  [ A_s]    NEG         A_l_tmp,    A_l_tmp               ; if(sign) -l_tmp
  [ B_nesc] MV          A_l_tmp,    A_level               ; if(nesc) level=l_tmp
                                                          
                                                          
            ROTL        B_dq,       0,          B_dq_s                
  [!A_s]    NEG         B_dq,       B_dq_s                ; if (!s) dqs= -dqs
                                                          
            LDW         *+B_buf[2],             B_t_w1    ; Load next word
                                                          
            CMPGT       B_bit,      B_nbit,     B_nc1     ; nc1 = (bit<nbit)
            SUB         B_bit,      B_nbit,     B_bit     ; bit -= nbit
  [!B_nc1]  MV          B_w1,       B_w0                  ; if (!nc1) w0 = w1
  [!B_nc1]  MV          B_t_w1,     B_w1                  ; if (!nc1) w1 = w1_t
  [!B_nc1]  ADD         B_buf,      4,          B_buf     ; if (!nc)  buf += 4
  [!B_nc1]  ADD         B_bit,      B_c32,      B_bit     ; if (!nc)  bit += 32
                                                          
            SUB         B_c32,      B_bit,      B_sl      ; sl = 32 - bit
            SHL         B_w0,       B_sl,       B_w0_     ; w0_ = w0 << sl
            SHRU        B_w1,       B_bit,      B_w1_     ; w1- = w1 >> bit
            ADD         B_w0_,      B_w1_,      B_vld_buf ; w0_ + w1_
                                                          
            ADD         A_zz,       1,          A_zz      ; zz++
            LDB         *++A_zz[A_run],         B_idx     ; idx = zz[run]
                                                          
            CMPGTU      A_zz,       A_zz_end,   A_err1    ; err2 = zz < zz_end
            OR          A_err1,     A_err2,     A_err     ;
                                                          
            MPY         A_Q,        A_level,    A_levelQ  ; levelQ = level*Q
            ADD         B_dq_s,     A_levelQ,   B_levelQ  ; levelQ += dQ
                                                          
            ADD         A_err,      A_last,     A_EOB     ; EOB = last + error
                                                
  [!A_err]  STH         B_levelQ,   *+B_idct[B_idx  ]     ; if (!err) store

  [!A_EOB]  B           dectcoef_loop                     ; if (!EOB) Branch
                                                        
                                                        
            STW         B_buf,    *A_bufPtr               ; Store buffer pointer
            STW         B_bit,    *B_bitPtr               ; Store bit pointer

            .return     A_err                             ; return err_sum
            .endproc

* ========================================================================= *
*   End of file:  h263_vld_n.sa                                             *
* ------------------------------------------------------------------------- *
*             Copyright (c) 1999 Texas Instruments, Incorporated.           *
*                            All Rights Reserved.                           *
* ========================================================================= *