mpeg2_vld_intra_h.asm

h263,jpeg,mpeg2编解码核心程序(TI DSP C64xx)

||      SUB     .D1     A_const32,  A_len,      A_len_c         ;[10,2] 

        EXTU    .S2     B_top0_bk,  6,  26,     B_run           ;[21,1] 
||[B_test3]MPY  .M2     B_rld_left, 0,          B_rld_left      ;[11,2] 
||      MV      .L2X    A_top0_bk,  B_top0_bk                   ;[11,2] 
||      AND     .S1     A_const31,  A_bptr1,    A_bptr          ;[11,2] 
||      MV      .D1     A_ptop0h,   A_top0h                     ;[11,2] 
||      NORM    .L1     A_ptop0h:A_ptop0l,      A_nrm           ;[ 1,3] 

        MPY     .M2     B_level,    2,          B_level2        ;[22,1] 
||      CMPGT   .L1     A_bptr1,    A_const31,  A_test2         ;[12,2] 
||      MPY     .M1     A_nrm,      -16,        A_t2            ;[ 2,3] 
||      SHL     .S1     A_ptop0h:A_ptop0l, A_nrm, A_t1h:A_t1l   ;[ 2,3] 
||      LDW     .D1T2   *+A_Mpeg2v[ZPTR_M2OFF], B_Zptr          ;reset
||      MVK     .S2     63,         B_const63                   ;const
||      MV      .L2     B_bsbuf_circ,           B_bsbuf_circ_bk ;preserve

        LDH     .D2T1   *++B_Wptr[B_run],       A_W             ;[23,1] 
||      CMPLT   .L1X    B_level,    0,          A_neg           ;[23,1] 
||      SHL     .S2     B_top0_bk,  B_rld_left, B_t13           ;[13,2] 
||      MPY     .M2X    B_const32,  A_len,      B_t12           ;[13,2] 
||      MV      .L2     B_word2,    B_word2_bk                  ;preserve
||      MV      .D1     A_word1,    A_word1_bk                  ;preserve
||      MVD     .M1     A_word1_rw, A_word1_rw_bk               ;preserve

        ADD     .L2     B_Wptr,     2,          B_Wptr          ;[24,1] 
||      ADD     .D1X    A_t8,       B_t9,       A_top1          ;[24,1] 
||      SHRU    .S2     B_t13,      27,         B_t14           ;[14,2]  
||[ A_test2]LDW .D2T2   *B_bsbuf_circ++,        B_word2         ;[14,2] 
||      SHRU    .S1     A_t1h:A_t1l, A_const36, A_t4h:A_t4l     ;[ 4,3] 
||      SUB     .L1     A_len_tbl_adr,          A_t2,       A_t3;[ 4,3] 

  [ A_neg]SUB   .D2     B_level2,   0,          B_level3        ;[25,1]  
||      ADD     .L2     B_t14,      B_t12,      B_t15           ;[15,2] 
||      SUB     .S2X    B_const32,  A_bptr,     B_bptr_cmpl     ;[15,2] 
||[ A_test2]MV  .L1X    B_word2,    A_word1                     ;[15,2] 
|| [A_test2]MV  .S1     A_word1,    A_word1_rw                  ; RWD
||      LDBU    .D1T1   *A_t3[A_t4l],           A_len           ;[ 5,3] 

  [!A_neg]ADD   .L2     B_level2,   0,          B_level3        ;[26,1]
||      ADD     .D2     B_t15,      B_t15,      B_t16           ;[16,2] 
||      SUB     .D1     A_len,      24,         A_test1         ;[16,2] 
||      SHRU    .S1     A_top1,     A_len_c,    A_t7            ;[16,2] 

        CMPGT   .L2     B_run,      B_const63,  B_eob           ;[27,1] 
||[ A_test1]LDB .D2T2   *B_rld_table_adr[B_t16],B_level         ;[17,2] 
||      ADD     .D1     A_ptop0l,   A_t7,       A_top0l         ;[17,2] 
||      ADD     .S2     B_Zptr,     1,          B_Zptr          ;reset
||      MV      .L1X    B_outi,     A_outi                      ; 12Q4

* =========================== PIPE LOOP KERNEL ============================ *
        .asg    A2,     A2_top0l 
        .asg    B31,    B_run_bk

loop:
        MPY     .M1     A_qscl,     A_W,        A_qw            ;[28,1] 
||[!B_eob]CMPGT .L2     B_Wptr,     B_Wptr_end, B_eob           ;[28,1] 
||[A_test1]LDB  .D2T2   *B_rld_table_adr_1[B_t16],      B_run   ;[18,2] 
||      EXT     .S2     B_top0_bk,  12, 20,    B_level          ;[18,2] 
||      SHRU    .S1     A_top0h:A_top0l, 8,    A_empty:A_top0_bk;[ 8,3] 
||[B_eob]MPY    .M2     0,          B_Wptr,     B_Wptr          ;err det

        LDB     .D2T1   *++B_Zptr[B_run],       A_cnum          ;[29,1] 
||      SHRU    .S2     B_word2,    B_bptr_cmpl,B_t9            ;[19,2] 
||      SHL     .S1     A_word1,    A_bptr,     A_t8            ;[19,2] 
||[!B_eob]MV    .L1     A_top0h:A_top0l, A_top0h_bk:A_top0l_bk  ;preserve
||[B_eob]ADD    .L2     B_outi,     B_const63,  B_outi          ;mismatch
||[!B_eob]MPY   .M2X    1,          A_bptr,     B_bptr_bk       ;preserve

        ADD     .D2     B_Zptr,     1,          B_Zptr          ;[30,1] 
||      MPY     .M1X    A_qw,       B_level3,   A_level4        ;[30,1] 
||      SUB     .S2X    A_len,      5,          B_rld_left      ;[10,3] 
||      CMPLT   .L2X    A_len,      5,          B_test3         ;[10,3] 
||      ADD     .L1     A_bptr,     A_len,      A_bptr1         ;[10,3] 
||      SHL     .S1     A_top0h:A_top0l, A_len, A_ptop0h:A_ptop0l;[10,3] 
||      SUB     .D1     A_const32,  A_len,      A_len_c         ;[10,3] 
||[B_eob]MPY    .M2     1,          B_run,      B_run_bk        ;preserve

        EXTU    .S2     B_top0_bk,  6,  26,     B_run           ;[21,2] 
||[B_test3]MPY  .M2     B_rld_left, 0,          B_rld_left      ;[11,3] 
||      MV      .L2X    A_top0_bk,  B_top0_bk                   ;[11,3] 
||      AND     .S1     A_const31,  A_bptr1,    A_bptr          ;[11,3] 
||      MV      .D1     A_ptop0h,   A_top0h                     ;[11,3] 
||      NORM    .L1     A_ptop0h:A_ptop0l,      A_nrm           ;[ 1,4] 
||[B_eob]ADD    .D2     B_outi,     B_const63,  B_outi          ;mismatch

  [!B_eob]B     .S2     loop                                    ;[32,1] 
||[ A_neg]ADD   .D1     A_level4,   A_const31,  A_level4        ;[32,1] 
||      MPY     .M2     B_level,    2,          B_level2        ;[22,2] 
||      CMPGT   .L1     A_bptr1,    A_const31,  A_test2         ;[12,3] 
||      MPY     .M1     A_nrm,      -16,        A_t2            ;[ 2,4] 
||      SHL     .S1     A_ptop0h:A_ptop0l, A_nrm, A_t1h:A_t1l   ;[ 2,4] 
||[!B_eob]MV    .L2     B_bsbuf_circ,      B_bsbuf_circ_bk      ;preserve
||[B_eob]LDH    .D2T1   *B_outi,    A_last_coeff                ;mismatch

        SSHL    .S1     A_level4,   15,         A_level5        ;[33,1] 
||[!B_eob]LDH   .D2T1   *++B_Wptr[B_run],       A_W             ;[23,2] 
||      CMPLT   .L1X    B_level,    0,          A_neg           ;[23,2] 
||      SHL     .S2     B_top0_bk,  B_rld_left, B_t13           ;[13,3] 
||      MPY     .M2X    B_const32,  A_len,      B_t12           ;[13,3] 
||[!B_eob]MV    .L2     B_word2,    B_word2_bk                  ;preserve
||[!B_eob]MV    .D1     A_word1,    A_word1_bk                  ;preserve
||[!B_eob]MVD   .M1     A_word1_rw, A_word1_rw_bk               ;preserve

  [!B_eob]ADD   .L2     B_Wptr,     2,          B_Wptr          ;[24,2] 
||[!B_eob]ADD   .D1X    A_t8,       B_t9,       A_top1          ;[24,2]  
||      SHRU    .S2     B_t13,      27,         B_t14           ;[14,3]  
||[ A_test2]LDW .D2T2   *B_bsbuf_circ++,        B_word2         ;[14,3] 
||      SHRU    .S1     A_t1h:A_t1l, A_const36, A_t4h:A_t4l     ;[ 4,4] 
||      SUB     .L1     A_len_tbl_adr,          A_t2,       A_t3;[ 4,4] 

        SHR     .S1     A_level5,   A_constSHR, A_level_f       ;[35,1] 12Q4 MERGE
||[ A_neg]SUB   .D2     B_level2,   0,          B_level3        ;[25,2] 
||      ADD     .L2     B_t14,      B_t12,      B_t15           ;[15,3]
||      SUB     .S2X    B_const32,  A_bptr,     B_bptr_cmpl     ;[15,3] 
||[ A_test2]MV  .L1X    B_word2,    A_word1                     ;[15,3] 
|| [A_test2]MVD .M1     A_word1,    A_word1_rw                  ; RWD
||      LDBU    .D1T1   *A_t3[A_t4l],           A_len           ;[ 5,4] 

  [!A_neg]ADD   .L2     B_level2,   0,          B_level3        ;[26,2] 
||      ADD     .S2     B_t15,      B_t15,      B_t16           ;[16,3] 
||      SUB     .D1     A_len,      24,         A_test1         ;[16,3] 
||      SHRU    .S1     A_top1,     A_len_c,    A_t7            ;[16,3] 
||[!B_eob]AND   .L1X    B_constFFF0,A_level_f,  A_level_f       ; 12Q4

  [!B_eob]STH   .D1T1   A_level_f,  *+A_outi[A_cnum]            ;[36,1] BC 
||[!B_eob]ADD   .S2X    B_sum,      A_level_f,  B_sum           ;[37,1] 
||        CMPGT .L2     B_run,      B_const63,  B_eob           ;[27,2] 
||[ A_test1]LDB .D2T2   *B_rld_table_adr[B_t16],B_level         ;[17,3] 
||[!B_eob]ADD   .L1     A_ptop0l,   A_t7,       A2_top0l        ;[17,3]
||[B_eob] XOR   .S1     A_const16,  A_last_coeff, A_last_coeff  ;mismatch
||[B_eob] MVD   .M1     A_word1_rw_bk,          A_word1_rw      ; RWD

* =========================== PIPE LOOP EPILOG ============================ *
* ========================================================================= *
; live-out: top0h:top0k, top1, word1, word2, bsbuf_circ, run, Wptr, Wptr_end, 
;           sum, bptr

    .asg    B0,     B_err       ; same reg as B_eob
    .asg    A29,    A_Mpeg2v
    .asg    B31,    B_bsbuf
    .asg    B3,     B_ret       ; Return address
    .asg    B15,    B_SP        ; Stack pointer, B datapath
    .asg    B1,     B_const65

mismatch: 
 [B_cnt] B       .S1     block_loop                             ; -- BRANCH --
||       MVK     .S2     65,           B_const65                ; invalid VLC
||       CMPGTU  .L2     B_Wptr,       B_Wptr_end, B_err        ; overrun
||       AND     .L1X    A_const16,    B_sum,      A_odd        ;mismatch

 [!B_err]CMPGT   .L2     B_run_bk,     B_const65,  B_err        ; invalid VLC
||       ADD     .S2     B_outi,       2,          B_outi
||       LDW     .D1T2   *+A_Mpeg2v[BSBUF_M2OFF],  B_bsbuf      ; exit
||       MVK     .S1     32,           A_const32                ; exit
||[!A_odd]STH    .D2T1   A_last_coeff, *B_outi                  ; mismatch 

 [B_err] B       .S2     exit                                   ; -- BRANCH --
||       LDW     .D2T2   *+B_SP[2],    B_ret                    ; exit
||       MV      .L2     B_bsbuf_circ_bk, B_bsbuf_circ          ; AMR arg

         NOP             3 
; branch occurs to block_loop 
         NOP             2 
; branch occurs to exit after 2 cycles in block_loop 
; (preserve B0_err for exit)

* =================================== EXIT =============================== *
        .asg            B26,        B_csr        ; CSR value to restore
        .asg            B22,        B_byte_diff
        .asg            B29,        B_next_wptr
        .asg            B1,         B_lz
        .asg            B27,        B_amr_config
        .asg            B4,         B_constBUFMASK                
        .asg            A14,        A_SP                     ; 12Q4 MERGE

exit:
        SUB     .L2      B_bsbuf_circ,  B_bsbuf, B_byte_diff
||      SHRU    .S1      A_top1,        8,         A_t2
||      SUB     .S2      B_bptr_bk,     8,         B_bptr_bk   
||      LDW     .D2T1    *+B_SP[6], A13                      ; 12Q4
||      MV      .L1X     B_SP,            A_SP               ; 12Q4 MERGE
        
        SHR     .S2      B_byte_diff,   2,         B_next_wptr
||      SHL     .S1      A_top0l_bk,    24,        A_t3
||      CMPLT   .L2      B_bptr_bk,     0,         B_lz
||      LDW     .D2T2    *+B_SP[1],     B14
||      LDW     .D1T1    *+A_SP[7],     A14                 ; 12Q4 MERGE          

        ADD     .L1      A_t2,          A_t3,      A_top1
||      SHRU    .S1      A_top0h_bk:A_top0l_bk, 8, A_empty:A_top0_bk
||      STW     .D1T2    B_err,      *+A_Mpeg2v[FAULT_M2OFF]
||[B_lz]MVD     .M1      A_word1_rw,               A_word1_bk   ; RWD
||[B_lz]MV      .L2X     A_word1_bk,               B_word2_bk
||      LDW     .D2T1    *+B_SP[4], A11                      ; 12Q4
 
        LDW     .D2T2    *+B_SP[3],     B_csr        ; Get CSR's value 
||      STW     .D1T1    A_top1,        *+A_Mpeg2v[TOP1_M2OFF]       
||[B_lz]ADD     .L2      B_bptr_bk,     A_const32, B_bptr_bk

        STW     .D1T2    B_bptr_bk,     *+A_Mpeg2v[BPTR_M2OFF]       
||      LDW     .D2T1    *+B_SP[5], A12                      ; 12Q4

        B       .S2      B_ret                       ; Return to caller
||      STW     .D1T1    A_top0_bk,     *+A_Mpeg2v[TOP0_M2OFF]
||[B_lz]SUBAW   .D2      B_bsbuf_circ, 1, B_bsbuf_circ    ; AMR arg

        LDW     .D2T1    *++B_SP[10],   A10          ; 2 W-mat
||      ZERO    .S2      B_amr_config
||[B_lz]SUB     .L2      B_bsbuf_circ,  B_bsbuf, B_byte_diff  ; AMR arg
        
        STW     .D1T1    A_word1_bk,    *+A_Mpeg2v[WORD1_M2OFF]
||[B_lz]SHR     .S2      B_byte_diff,   2,         B_next_wptr  ; AMR arg
        
        STW     .D1T2    B_word2_bk,    *+A_Mpeg2v[WORD2_M2OFF]
||      MVC     .S2      B_csr,         CSR           ; Restore CSR
;  ===== Interruptibility state restored here =====

        STW     .D1T2    B_next_wptr,   *+A_Mpeg2v[NEXTWPTR_M2OFF] ; AMR arg
||      MVC     .S2      B_amr_config,  AMR

        NOP
; Branch occurs

* ========================================================================= *
*   End of file:   mpeg2_vld_intra_h.asm                                    *
* ------------------------------------------------------------------------- *
*             Copyright (c) 2001 Texas Instruments, Incorporated.           *
*                            All Rights Reserved.                           *
* ========================================================================= *