📄 mpeg2_vld_intra_h.asm
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.asg A26, A_t4l .asg A27, A_t1h .asg A27, A_t4h .asg A3, A_top0h .asg A4, A_ptop0l .asg A5, A_level5 .asg A5, A_level_f .asg A5, A_ptop0h .asg A6, A_W .asg A7, A_top1 .asg A8, A_word1 .asg A9, A_t3 .asg A9, A_t7 .asg A9, A_t8 .asg B0, B_eob .asg B1, B_run .asg B1, B_test3 .asg B16, B_level2 .asg B16, B_rld_left .asg B17, B_bptr_cmpl .asg B17, B_t14 .asg B17, B_t9 .asg B18, B_cnum .asg B19, B_word2 .asg B2, B_cnt .asg B20, B_Wptr_end .asg B21, B_Zptr .asg B22, B_outi .asg B23, B_sum .asg B24, B_top0_bk .asg B26, B_level3 .asg B3, B_const63 .asg B4, B_rld_table_adr .asg B5, B_const32 .asg B6, B_rld_table_adr_1 .asg B7, B_bsbuf_circ .asg B8, B_Wptr .asg B9, B_level .asg B9, B_t12 .asg B9, B_t13 .asg B9, B_t15 .asg B9, B_t16 .asg A11, A_outi ; 12Q4 .asg A12, A_cnum ; 12Q4 .asg A13, A_const16 ; 12Q4 .asg B18, B_constFFF0 ; 12Q4 .asg A2, A_12Q4 ; 12Q4 MERGE* ========================================================================= * .global _IMG_len_tbl0 .global _IMG_rld_table0 .global _IMG_len_tbl1 .global _IMG_rld_table1; Mpeg2v structure:BSBUF_M2OFF .set 0x0NEXTWPTR_M2OFF .set 0x1BPTR_M2OFF .set 0x2WORD1_M2OFF .set 0x3WORD2_M2OFF .set 0x4TOP0_M2OFF .set 0x5TOP1_M2OFF .set 0x6ZPTR_M2OFF .set 0x7FORMAT_M2OFF .set 0x8QSCL_M2OFF .set 0x9DCPREC_M2OFF .set 0xACBP_M2OFF .set 0xBFAULT_M2OFF .set 0xC_mpeg2_vld_intra_asm:; parameters: B_Wptr, B_outi, A_Mpeg2v, B_dc_pred, A_12Q4, B_num_blocks, A_bsbuf_words; A4, B4, A6, B6, A8, B8, A10* ========================================================================= ** Setup* ========================================================================= * .asg B15, B_SP ; Stack pointer, B datapath .asg B0, B_csr ; CSR's value .asg B1, B_no_gie ; CSR w/ GIE bit cleared .asg B3, B_ret ; Return address .asg A29, A_Mpeg2v .asg B18, B_Mpeg2v .asg B14, B_dc_pred .asg A10, A_amr_arg ; AMR arg .asg A3, A_const32 ; AMR arg STW .D2T1 A10, *B_SP--[10] ; RWD, 2 W-mat || MVC .S2 CSR, B_csr ; Get CSR's state|| MV .L2 B4, B_outi || MV .L1 A6, A_Mpeg2v|| MV .D1 A8, A_12Q4 ; 12Q4 MERGE STW .D2T2 B_csr, *+B_SP[3] ; Save CSR || AND .L2 B_csr, -2, B_no_gie ; Clear GIE|| MV .S2 B8, B_cnt ; 2 W-mat|| LMBD .L1 1, A_amr_arg, A_amr_arg; AMR arg|| MVK .S1 32, A_const32 ; AMR arg STW .D2T2 B14, *+B_SP[1] || MV .L2 B6, B_dc_pred|| MV .S2X A6, B_Mpeg2v|| SUB .L1 A_const32, A_amr_arg, A_amr_arg; AMR arg STW .D2T2 B_ret, *+B_SP[2] ; Save return addr.|| MVC .S2 B_no_gie, CSR ; Disable ints.|| MV .L2X A4, B_Wptr ; 2 W-mat|| SHL .S1 A_amr_arg, 16, A_amr_arg; AMR arg; ===== Interrupts masked here ===== * ========================================================================= ** Get bitstream info* Setup circuar bitstream buffer* Load table addresses and constants* Block loop setup* ========================================================================= * .asg B31, B_bsbuf .asg B29, B_next_wptr .asg B27, B_cbp .asg B0, B0_amr_config .asg A21, A_const1 .asg A9, A_tbs1 .asg A4, A_tbs2 .asg B17, B_tbs3 .asg B3, B_const126 .asg B3, B_const128 .asg A0, A_if ; intra_vlc_format .asg B26, B_num_blocks ; 2 W-mat .asg B26, B_non420 ; 2 W-mat LDW .D2T2 *+B_Mpeg2v[BSBUF_M2OFF], B_bsbuf|| LDW .D1T1 *+A_Mpeg2v[TOP0_M2OFF], A_top0_bk || MVK .S2 128, B_const128 || SET .S1 A_amr_arg, 14, 14, A_amr_arg ; AMR arg LDW .D2T2 *+B_Mpeg2v[CBP_M2OFF], B_cbp|| LDW .D1T1 *+A_Mpeg2v[TOP1_M2OFF], A_top1 || MVC .S2X A_amr_arg, AMR ; AMR arg LDW .D2T2 *+B_Mpeg2v[NEXTWPTR_M2OFF], B_next_wptr|| LDW .D1T1 *+A_Mpeg2v[BPTR_M2OFF], A_bptr|| ADD .L2 B_Wptr, B_const128, B_Wptr_end LDW .D1T1 *+A_Mpeg2v[WORD1_M2OFF], A_word1 LDW .D2T2 *+B_Mpeg2v[WORD2_M2OFF], B_word2|| LDW .D1T1 *+A_Mpeg2v[FORMAT_M2OFF], A_if|| MVK .S1 31, A_const31 * ========================================================================= ** Setup bitstream pointers: top0h:top0l, top1 contain top bitstream* ========================================================================= * .asg B25, B_word2_bk .asg A28, A_word1_bk .asg A10, A_word1_rw ; RWD .asg A21, A_word1_rw_bk ; RWD .asg A31, A_top0h_bk .asg A30, A_top0l_bk .asg B28, B_bptr_bk .asg B30, B_bsbuf_circ_bk SHL .S1 A_top0_bk, 8, A_tbs1|| STW .D2T1 A11, *+B_SP[4] ; 12Q4||[A_12Q4]MVKL .S2 0xFFF0, B_constFFF0 ; 12Q4 MERGE SHRU .S1 A_top1, 24, A_tbs2|| STW .D2T1 A12, *+B_SP[5] ; 12Q4||[!A_12Q4]MVKL .S2 0xFFFF, B_constFFF0 ; non-12Q4 MERGE ADD .L1 A_tbs1, A_tbs2, A_top0l_bk|| ADD .D1 A_bptr, 8, A_bptr1|| STW .D2T1 A13, *+B_SP[6] ; 12Q4||[A_12Q4]MVK .S1 16, A_const16 ; 12Q4 MERGE CMPGT .L1 A_bptr1, A_const31, A_test2|| AND .S1 A_bptr1, A_const31, A_bptr|| MVK .S2 32, B_const32|| ADDAW .D2 B_bsbuf, B_next_wptr,B_bsbuf_circ ||[!A_12Q4]MVK .D1 1, A_const16 ; non-12Q4 MERGE [A_test2]MV .S1 A_word1, A_word1_rw ; RWD||[A_test2]MV .L1X B_word2, A_word1||[A_test2]LDW .D2T2 *B_bsbuf_circ++, B_word2|| SUB .S2 B_const32, A_bptr, B_bptr_cmpl [!A_if]MVKL .S1 _IMG_len_tbl0, A_len_tbl_adr ||[!A_if]MVKL .S2 _IMG_rld_table0, B_rld_table_adr|| MV .L2X A_bptr, B_bptr_bk|| STW .D2T1 A14, *+B_SP[7] ; 12Q4 MERGE|| MVK .L1 15, A_constSHR ; 12Q4 MERGE [!A_if]MVKH .S1 _IMG_len_tbl0, A_len_tbl_adr||[!A_if]MVKH .S2 _IMG_rld_table0, B_rld_table_adr||[A_12Q4]ADD .L1 A_constSHR, 1, A_constSHR ;(16) 12Q4 MERGE [A_if]MVKL .S1 _IMG_len_tbl1, A_len_tbl_adr ||[A_if]MVKL .S2 _IMG_rld_table1, B_rld_table_adr||[!A_12Q4]ADD .L1 A_constSHR, 5, A_constSHR ;(20) 12Q4 MERGE [A_if]MVKH .S1 _IMG_len_tbl1, A_len_tbl_adr||[A_if]MVKH .S2 _IMG_rld_table1, B_rld_table_adr|| ADD .L2 B_Wptr, 2, B_Wptr ; 2 W-mat SHL .S1 A_word1, A_bptr, A_tbs1|| SHRU .S2 B_word2, B_bptr_cmpl,B_tbs3|| SUB .L2 B_cnt, 1, B_num_blocks ; 2 W-mat|| STW .D2T2 B_Wptr, *+B_SP[9] ; base+2 of W-mat ADD .L1X A_tbs1, B_tbs3, A_top1 || SHRU .S1 A_top0_bk, 24, A_top0h_bk|| MV .D1 A_word1, A_word1_bk|| MV .S2 B_word2, B_word2_bk|| MV .L2 B_bsbuf_circ, B_bsbuf_circ_bk|| STW .D2T2 B_num_blocks, *+B_SP[8] ; 2 W-matblock_loop:* ------------------------------------------------------------------------- ** check cbp, etc.* ------------------------------------------------------------------------- * .asg B17, B_cbp_mask .asg B0, B_coded .asg A5, A_last_coeff .asg A0, A_odd SUB .S2 B_cnt, 1, B_cnt ; cbp, cnt--|| ZERO .L2 B_sum|| ZERO .L1 A_odd ; not coded|| MVK .S1 1, A_const1 || LDW .D2T2 *+B_SP[8], B_num_blocks ; 2 W-mat SHL .S2X A_const1, B_cnt, B_cbp_mask ; cbp⌨️ 快捷键说明
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