📄 mpeg2_vld_inter_n.sa
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* coded block pattern * ------------------------------------------------------------------------- * .reg cbp, bcomp, cbp_mask, coded* ------------------------------------------------------------------------- ** Decoding of the first coefficient * ------------------------------------------------------------------------- * .reg tm* ------------------------------------------------------------------------- ** 32-bit words at 32-bit boundaries from bitstream buffer bsbuf[] * ------------------------------------------------------------------------- * .reg bsbuf, word0, word1, word2, next_wptr, byte_diff .reg word1_rw * ------------------------------------------------------------------------- ** bptr points to the current bit position within the current 32-bit* aligned word* ------------------------------------------------------------------------- * .reg bptr, bptr1, bptr_cmpl, bptr0, bptr0_cmpl .reg e0, e1, bptr_adj, lz * ------------------------------------------------------------------------- ** top0 and top1 contain the bitstream aligned at the beginning of the* VLC to decode* ------------------------------------------------------------------------- * .reg empty1:top0, top0h:top0l, top1, empty:top0_bk .reg at1h:at1l, at2, at3, at4h:at4l, at6h:at6l, at7, at8, at9 .reg more * ------------------------------------------------------------------------- ** Variables for length, run and level decoding* ------------------------------------------------------------------------- * .reg len_tbl_adr, len_c_tbl_adr .reg t1, t2, t4, t4b, t5, t7, t8, t9 .reg sign, rld_left, rld_table_adr, rld_table_adr_1 .reg run_level .reg run, run_bk, len, len_c, len_1 .reg t3, t3b .reg level .reg s1, s2, s3, s4, s5, s6, eob_err, nrm, fault .reg no_esc, test2, test3 * ------------------------------------------------------------------------- ** Variables for de-quantization* ------------------------------------------------------------------------- * .reg level2, level3, level4, level5, level_f .reg neg, pos, f1, f3, f5, f4, qW, sum, odd, last_coeff .reg Wptr_origin, Wptr_end, Zptr_origin, Zptr .reg W, Z, qscl * ------------------------------------------------------------------------- ** Variables for 12Q4 * ------------------------------------------------------------------------- * .reg mism_bit, shift_12Q4, mask_12Q4, level6 * ------------------------------------------------------------------------- ** Variables for 4:2:2 and 4:4:4 support * ------------------------------------------------------------------------- * .reg cc, chrom_mat * ========================================================================= ** Get bitstream info* ========================================================================= * LDW *+Mpeg2v[0], bsbuf LDW *+Mpeg2v[1], next_wptr LDW *+Mpeg2v[2], bptr LDW *+Mpeg2v[3], word1 LDW *+Mpeg2v[4], word2 LDW *+Mpeg2v[5], top0 LDW *+Mpeg2v[6], top1 LDW *+Mpeg2v[7], Zptr LDW *+Mpeg2v[9], qscl LDW *+Mpeg2v[11], cbp* ========================================================================= ** Setup* ========================================================================= * MVKL _IMG_len_tbl0, len_tbl_adr ; length table MVKH _IMG_len_tbl0, len_tbl_adr MVKL _IMG_rld_table0, rld_table_adr MVKH _IMG_rld_table0, rld_table_adr ADD 1, rld_table_adr, rld_table_adr_1 [!m12Q4]MVK 1, mism_bit [!m12Q4]MVK 20, shift_12Q4 [!m12Q4]MVKL 0xFFFF, mask_12Q4 [m12Q4] MVK 16, mism_bit [m12Q4] MVK 16, shift_12Q4 [m12Q4] MVKL 0xFFF0, mask_12Q4 MVK 1, const1 MVK 24, const24 MVK 31, const31 MVK 32, const32 MVK 36, const36 MVK 63, const63 MVK 65, const65 MVK 128, const128 ADD Wptr, const128, Wptr_end MV Wptr, Wptr_origin MV Zptr, Zptr_origin MVC CSR, csr_bk AND csr_bk, -2, no_gie ; disable all interrupts MVC no_gie, CSR* ========================================================================= ** Setup bitstream pointers: top0h:top0l, top1 contain top bitstream* ========================================================================= * .reserve A5 LMBD 1, bsbuf_size, amr_config SUB const32, amr_config, amr_config SHL amr_config, 16, amr_config ADD amr_config, 4, amr_config MVC amr_config, AMR ADDAW bsbuf, next_wptr, A5 SHRU top0, 24, top0h SHL top0, 8, t5 SHRU top1, 24, t7 ADD t5, t7, top0l ADD bptr, 8, bptr1 CMPGT bptr1, const31, test2 [test2] MV word1, word1_rw[test2] MV word2, word1[test2] LDW *A5++, word2 AND bptr1, const31, bptr SUB const32, bptr, bptr_cmpl SHL word1, bptr, t8 SHRU word2, bptr_cmpl, t9 ADD t8, t9, top1 * ========================================================================= ** Block loop setup* ========================================================================= * SUB num_blocks, 1, num_blocks MV num_blocks, cnt ; dec cnt for block loop ZERO fault block_loop: SHL const1, cnt, cbp_mask AND cbp_mask, cbp, coded ZERO sum[!coded] ADD outi, const128, outi ; start of next 8x8 block[!coded] B cont MV Zptr_origin, Zptr ; reset Zptr MV Wptr_origin, Wptr ; reset Wptr SUB num_blocks, cnt, block CMPLT block, 4, flag ; determine cc ZERO cc[!flag] AND block, 1, cc[!flag] ADD cc, 1, cc ZERO chrom_mat [cc] CMPGT num_blocks, 5, chrom_mat [chrom_mat]ADD Wptr_origin, const128, Wptr ADD Wptr, const128, Wptr_end ZERO eob_err * ========================================================================= ** Decode first coefficient * ========================================================================= * SHRU top0h, 7, tm[!tm] B ac_loop_init* ------------------------------------------------------------------------- ** Length computation: len=2, len_c=30* ------------------------------------------------------------------------- ** ------------------------------------------------------------------------- ** advance bitstream * ------------------------------------------------------------------------- * SHL top0h:top0l, 2, at6h:at6l SHRU top1, 30, at7 ADD at6l, at7, top0l ADD bptr, 2, bptr1 CMPGT bptr1, const31, test2 [test2] MV word1, word1_rw[test2] MV word2, word1[test2] LDW *A5++, word2 AND bptr1, const31, bptr SUB const32, bptr, bptr_cmpl SHL word1, bptr, at8 SHRU word2, bptr_cmpl, at9 ADD at8, at9, top1 ⌨️ 快捷键说明
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