decoder.vhd

数字秒表的设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (din:in std_logic_vector(3 downto 0 );   --四位二进制码输入
dout:out std_logic_vector(6 downto 0) );  --输出LED七段码
end decoder;
architecture Behavioral of decoder is
begin
process(din)
begin
case din is
when "0000" => dout<="0111111";--0
when "0001" => dout<="0000110";--1
when "0010" => dout<="1011011";--2
when "0011" => dout<="1001111";--3
when "0100" => dout<="1100110";--4
when "0101" => dout<="1101101";--5
when "0110" => dout<="1111101";--6
when "0111" => dout<="0000111";--7
when "1000" => dout<="1111111";--8
when "1001" => dout<="1101111";--9
when others => dout<="0000000";
end case;
end process;
end Behavioral;