time.map.qmsg

数字秒表的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 23 16:29:36 2008 " "Info: Processing started: Mon Jun 23 16:29:36 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off time -c time " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off time -c time" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt-art " "Info: Found design unit 1: cnt-art" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt " "Info: Found entity 1: cnt" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkgen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkgen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clkgen-behavioral " "Info: Found design unit 1: clkgen-behavioral" {  } { { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clkgen " "Info: Found entity 1: clkgen" {  } { { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "time.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file time.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 time " "Info: Found entity 1: time" {  } { { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xianshi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file xianshi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xianshi-behav " "Info: Found design unit 1: xianshi-behav" {  } { { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 xianshi " "Info: Found entity 1: xianshi" {  } { { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-Behavioral " "Info: Found design unit 1: decoder-Behavioral" {  } { { "decoder.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/decoder.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/decoder.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "time " "Info: Elaborating entity \"time\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:inst8 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:inst8\"" {  } { { "time.bdf" "inst8" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 40 752 896 136 "inst8" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xianshi xianshi:inst7 " "Info: Elaborating entity \"xianshi\" for hierarchy \"xianshi:inst7\"" {  } { { "time.bdf" "inst7" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 56 568 712 152 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt cnt:inst1 " "Info: Elaborating entity \"cnt\" for hierarchy \"cnt:inst1\"" {  } { { "time.bdf" "inst1" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 240 240 360 336 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkgen clkgen:inst " "Info: Elaborating entity \"clkgen\" for hierarchy \"clkgen:inst\"" {  } { { "time.bdf" "inst" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 88 240 352 184 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt cnt:inst4 " "Info: Elaborating entity \"cnt\" for hierarchy \"cnt:inst4\"" {  } { { "time.bdf" "inst4" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 232 568 688 328 "inst4" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cnt:inst6\|cqi\[3\] data_in GND " "Warning: Reduced register \"cnt:inst6\|cqi\[3\]\" with stuck data_in port to stuck value GND" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cnt:inst4\|cqi\[3\] data_in GND " "Warning: Reduced register \"cnt:inst4\|cqi\[3\]\" with stuck data_in port to stuck value GND" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "166 " "Info: Implemented 166 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "153 " "Info: Implemented 153 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 23 16:29:42 2008 " "Info: Processing ended: Mon Jun 23 16:29:42 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}