cnt.vhd

数字秒表的设计

--有时钟使能的十进制计数器的源程序CNT10.VHD
library ieee;
use ieee.std_logic_1164.all;
entity cnt is
generic(N:integer:=15);
port(clk:in std_logic; --计数时钟信号
     clr:in std_logic; --清零信号
     ena:in std_logic; --计数使能信号
     cq:out integer range 0 to 15; --4位计数结果输出
     carry_out:out std_logic);--计数进位
end cnt;
architecture art of cnt is
signal cqi:integer range 0 to 15;
begin
  process(clk,clr,ena)
    begin
      if clr='0' then cqi<=0;  --计数器异步清零
      elsif clk'event and clk='1' then
         if ena='1'then
            if cqi<N-1 then cqi<=cqi+1;
            else cqi<=0;
            end if;
         end if;
      end if;
  end process;
  process(cqi)
    begin
      if cqi=0 then carry_out<='1';--进位输出
      else carry_out<='0';
      end if;
  end process;
  cq<=cqi;
end art;