colorbar.fit.qmsg

源文件保存在src目录

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.582 ns register register " "Info: Estimated most critical path is register to register delay of 3.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[3\] 1 REG LAB_X43_Y20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X43_Y20; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.590 ns) 1.442 ns vga_vl:inst\|always4~149 2 COMB LAB_X42_Y19 2 " "Info: 2: + IC(0.852 ns) + CELL(0.590 ns) = 1.442 ns; Loc. = LAB_X42_Y19; Fanout = 2; COMB Node = 'vga_vl:inst\|always4~149'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "1.442 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.106 ns vga_vl:inst\|always4~152 3 COMB LAB_X42_Y19 1 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 2.106 ns; Loc. = LAB_X42_Y19; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~152'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.664 ns" { vga_vl:inst|always4~149 vga_vl:inst|always4~152 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 2.770 ns vga_vl:inst\|always4~153 4 COMB LAB_X42_Y19 1 " "Info: 4: + IC(0.550 ns) + CELL(0.114 ns) = 2.770 ns; Loc. = LAB_X42_Y19; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~153'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.664 ns" { vga_vl:inst|always4~152 vga_vl:inst|always4~153 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 3.582 ns vga_vl:inst\|enable 5 REG LAB_X42_Y19 5 " "Info: 5: + IC(0.074 ns) + CELL(0.738 ns) = 3.582 ns; Loc. = LAB_X42_Y19; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.812 ns" { vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.734 ns 48.41 % " "Info: Total cell delay = 1.734 ns ( 48.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.848 ns 51.59 % " "Info: Total interconnect delay = 1.848 ns ( 51.59 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "3.582 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 12 11:44:19 2006 " "Info: Processing ended: Tue Sep 12 11:44:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}