colorbar.fit.qmsg

源文件保存在src目录

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 12 11:44:06 2006 " "Info: Processing started: Tue Sep 12 11:44:06 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ColorBar -c ColorBar" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ColorBar EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"ColorBar\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "VGA_PLL:inst4\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"VGA_PLL:inst4\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 4 5 0 0 " "Info: Implementing clock multiplication of 4, clock division of 5, and phase shift of 0 degrees (0 ps) for VGA_PLL:inst4\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_PLL.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/VGA_PLL.v" 89 -1 0 } } { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } { 0 "VGA_PLL:inst4\|altpll:altpll_component\|_clk0" } } } } { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { -32 336 592 128 "inst4" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/ColorBar.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/ColorBar.fld" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga_vl:inst\|hsyncint Global clock " "Info: Automatically promoted some destinations of signal \"vga_vl:inst\|hsyncint\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "VGA_HS " "Info: Destination \"VGA_HS\" may be non-global or may not use global clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { 240 608 784 256 "VGA_HS" "" } } } }  } 0}  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { 240 104 272 256 "rst" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { 240 104 272 256 "rst" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { rst } "NODE_NAME" } "" } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/ColorBar.fld" "" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/ColorBar.fld" "" "" { rst } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}