colorbar.tan.qmsg

源文件保存在src目录

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_vl:inst\|hcnt\[10\] register vga_vl:inst\|hcnt\[10\] 1.079 ns " "Info: Minimum slack time is 1.079 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_vl:inst\|hcnt\[10\]\" and destination register \"vga_vl:inst\|hcnt\[10\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.870 ns + Shortest register register " "Info: + Shortest register to register delay is 0.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|hcnt\[10\] 1 REG LC_X40_Y19_N5 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y19_N5; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[10\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.309 ns) 0.870 ns vga_vl:inst\|hcnt\[10\] 2 REG LC_X40_Y19_N5 9 " "Info: 2: + IC(0.561 ns) + CELL(0.309 ns) = 0.870 ns; Loc. = LC_X40_Y19_N5; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[10\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.870 ns" { vga_vl:inst|hcnt[10] vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 35.52 % " "Info: Total cell delay = 0.309 ns ( 35.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.561 ns 64.48 % " "Info: Total interconnect delay = 0.561 ns ( 64.48 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.870 ns" { vga_vl:inst|hcnt[10] vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.870 ns" { vga_vl:inst|hcnt[10] vga_vl:inst|hcnt[10] } { 0.0ns 0.561ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.464 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.711 ns) 2.464 ns vga_vl:inst\|hcnt\[10\] 2 REG LC_X40_Y19_N5 9 " "Info: 2: + IC(1.753 ns) + CELL(0.711 ns) = 2.464 ns; Loc. = LC_X40_Y19_N5; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[10\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 28.86 % " "Info: Total cell delay = 0.711 ns ( 28.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.753 ns 71.14 % " "Info: Total interconnect delay = 1.753 ns ( 71.14 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 2.464 ns - Shortest register " "Info: - Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.711 ns) 2.464 ns vga_vl:inst\|hcnt\[10\] 2 REG LC_X40_Y19_N5 9 " "Info: 2: + IC(1.753 ns) + CELL(0.711 ns) = 2.464 ns; Loc. = LC_X40_Y19_N5; Fanout = 9; REG Node = 'vga_vl:inst\|hcnt\[10\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 28.86 % " "Info: Total cell delay = 0.711 ns ( 28.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.753 ns 71.14 % " "Info: Total interconnect delay = 1.753 ns ( 71.14 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.870 ns" { vga_vl:inst|hcnt[10] vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.870 ns" { vga_vl:inst|hcnt[10] vga_vl:inst|hcnt[10] } { 0.0ns 0.561ns } { 0.0ns 0.309ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hcnt[10] } { 0.0ns 1.753ns } { 0.0ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk VGA_VS vga_vl:inst\|vsync 11.992 ns register " "Info: tco from clock \"clk\" to destination pin \"VGA_VS\" through register \"vga_vl:inst\|vsync\" is 11.992 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk VGA_PLL:inst4\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { 24 104 272 40 "clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 9.190 ns + Longest register " "Info: + Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 9.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.935 ns) 2.688 ns vga_vl:inst\|hsyncint 2 REG LC_X28_Y17_N2 13 " "Info: 2: + IC(1.753 ns) + CELL(0.935 ns) = 2.688 ns; Loc. = LC_X28_Y17_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.688 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.791 ns) + CELL(0.711 ns) 9.190 ns vga_vl:inst\|vsync 3 REG LC_X42_Y19_N8 1 " "Info: 3: + IC(5.791 ns) + CELL(0.711 ns) = 9.190 ns; Loc. = LC_X42_Y19_N8; Fanout = 1; REG Node = 'vga_vl:inst\|vsync'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "6.502 ns" { vga_vl:inst|hsyncint vga_vl:inst|vsync } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 67 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 17.91 % " "Info: Total cell delay = 1.646 ns ( 17.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.544 ns 82.09 % " "Info: Total interconnect delay = 7.544 ns ( 82.09 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vsync } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vsync } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 67 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.632 ns + Longest register pin " "Info: + Longest register to pin delay is 4.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vsync 1 REG LC_X42_Y19_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y19_N8; Fanout = 1; REG Node = 'vga_vl:inst\|vsync'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { vga_vl:inst|vsync } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.508 ns) + CELL(2.124 ns) 4.632 ns VGA_VS 2 PIN PIN_169 0 " "Info: 2: + IC(2.508 ns) + CELL(2.124 ns) = 4.632 ns; Loc. = PIN_169; Fanout = 0; PIN Node = 'VGA_VS'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "4.632 ns" { vga_vl:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "../Src/ColorBar.bdf" "" { Schematic "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Src/ColorBar.bdf" { { 256 608 784 272 "VGA_VS" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.85 % " "Info: Total cell delay = 2.124 ns ( 45.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.508 ns 54.15 % " "Info: Total interconnect delay = 2.508 ns ( 54.15 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "4.632 ns" { vga_vl:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.632 ns" { vga_vl:inst|vsync VGA_VS } { 0.000ns 2.508ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vsync } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vsync } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "4.632 ns" { vga_vl:inst|vsync VGA_VS } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.632 ns" { vga_vl:inst|vsync VGA_VS } { 0.000ns 2.508ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 12 11:44:27 2006 " "Info: Processing ended: Tue Sep 12 11:44:27 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}