colorbar.tan.qmsg

源文件保存在src目录

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "vga_vl:inst\|hsyncint " "Info: Detected ripple clock \"vga_vl:inst\|hsyncint\" as buffer" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vga_vl:inst\|hsyncint" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 register vga_vl:inst\|vcnt\[3\] register vga_vl:inst\|enable 2.295 ns " "Info: Slack time is 2.295 ns for clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"vga_vl:inst\|vcnt\[3\]\" and destination register \"vga_vl:inst\|enable\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "49.0 MHz 20.41 ns " "Info: Fmax is 49.0 MHz (period= 20.41 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "5.513 ns + Largest register register " "Info: + Largest register to register requirement is 5.513 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "12.500 ns + " "Info: + Setup relationship between source and destination is 12.500 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 22.946 ns " "Info: + Latch edge is 22.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.446 ns " "Info: - Launch edge is 10.446 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_PLL:inst4\|altpll:altpll_component\|_clk0 25.000 ns 10.446 ns , Inverted 50 " "Info: Clock period of Source clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" is 25.000 ns with , Inverted offset of 10.446 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.726 ns + Largest " "Info: + Largest clock skew is -6.726 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.464 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.711 ns) 2.464 ns vga_vl:inst\|enable 2 REG LC_X42_Y19_N3 5 " "Info: 2: + IC(1.753 ns) + CELL(0.711 ns) = 2.464 ns; Loc. = LC_X42_Y19_N3; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 28.86 % " "Info: Total cell delay = 0.711 ns ( 28.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.753 ns 71.14 % " "Info: Total interconnect delay = 1.753 ns ( 71.14 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_PLL:inst4\|altpll:altpll_component\|_clk0 source 9.190 ns - Longest register " "Info: - Longest clock path from clock \"VGA_PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 9.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 13; CLK Node = 'VGA_PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { VGA_PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.935 ns) 2.688 ns vga_vl:inst\|hsyncint 2 REG LC_X28_Y17_N2 13 " "Info: 2: + IC(1.753 ns) + CELL(0.935 ns) = 2.688 ns; Loc. = LC_X28_Y17_N2; Fanout = 13; REG Node = 'vga_vl:inst\|hsyncint'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.688 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.791 ns) + CELL(0.711 ns) 9.190 ns vga_vl:inst\|vcnt\[3\] 3 REG LC_X43_Y20_N8 5 " "Info: 3: + IC(5.791 ns) + CELL(0.711 ns) = 9.190 ns; Loc. = LC_X43_Y20_N8; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "6.502 ns" { vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 17.91 % " "Info: Total cell delay = 1.646 ns ( 17.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.544 ns 82.09 % " "Info: Total interconnect delay = 7.544 ns ( 82.09 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.218 ns - Longest register register " "Info: - Longest register to register delay is 3.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vl:inst\|vcnt\[3\] 1 REG LC_X43_Y20_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y20_N8; Fanout = 5; REG Node = 'vga_vl:inst\|vcnt\[3\]'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "" { vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 90 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.281 ns) + CELL(0.292 ns) 1.573 ns vga_vl:inst\|always4~149 2 COMB LC_X42_Y19_N0 2 " "Info: 2: + IC(1.281 ns) + CELL(0.292 ns) = 1.573 ns; Loc. = LC_X42_Y19_N0; Fanout = 2; COMB Node = 'vga_vl:inst\|always4~149'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "1.573 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.442 ns) 2.431 ns vga_vl:inst\|always4~152 3 COMB LC_X42_Y19_N1 1 " "Info: 3: + IC(0.416 ns) + CELL(0.442 ns) = 2.431 ns; Loc. = LC_X42_Y19_N1; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~152'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.858 ns" { vga_vl:inst|always4~149 vga_vl:inst|always4~152 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.727 ns vga_vl:inst\|always4~153 4 COMB LC_X42_Y19_N2 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.727 ns; Loc. = LC_X42_Y19_N2; Fanout = 1; COMB Node = 'vga_vl:inst\|always4~153'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.296 ns" { vga_vl:inst|always4~152 vga_vl:inst|always4~153 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 3.218 ns vga_vl:inst\|enable 5 REG LC_X42_Y19_N3 5 " "Info: 5: + IC(0.182 ns) + CELL(0.309 ns) = 3.218 ns; Loc. = LC_X42_Y19_N3; Fanout = 5; REG Node = 'vga_vl:inst\|enable'" {  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "0.491 ns" { vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "../src/vga_vl.v" "" { Text "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/src/vga_vl.v" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.157 ns 35.95 % " "Info: Total cell delay = 1.157 ns ( 35.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns 64.05 % " "Info: Total interconnect delay = 2.061 ns ( 64.05 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "3.218 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.218 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 1.281ns 0.416ns 0.182ns 0.182ns } { 0.000ns 0.292ns 0.442ns 0.114ns 0.309ns } } }  } 0}  } { { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.464 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|enable } { 0.000ns 1.753ns } { 0.000ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.190 ns" { VGA_PLL:inst4|altpll:altpll_component|_clk0 vga_vl:inst|hsyncint vga_vl:inst|vcnt[3] } { 0.000ns 1.753ns 5.791ns } { 0.000ns 0.935ns 0.711ns } } } { "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" "" { Report "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar_cmp.qrpt" Compiler "ColorBar" "UNKNOWN" "V1" "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/db/ColorBar.quartus_db" { Floorplan "E:/EDA/cdrom/ALTERA/NIOS II开发板/HSNISO V3.2/EDA4.0底板PLD实验/ep1c12/VGA显示/Proj/" "" "3.218 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.218 ns" { vga_vl:inst|vcnt[3] vga_vl:inst|always4~149 vga_vl:inst|always4~152 vga_vl:inst|always4~153 vga_vl:inst|enable } { 0.000ns 1.281ns 0.416ns 0.182ns 0.182ns } { 0.000ns 0.292ns 0.442ns 0.114ns 0.309ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0}