📄 bcm.h
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//R
//BCM_ROM_SIG4
//-------------------
#define BCM_ROM_SIG4 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG4_OFFSET)
#define BCM_ROM_SIG4_RESERVED_POS 8
#define BCM_ROM_SIG4_RESERVED_NUMB 24
#define BCM_ROM_SIG4_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG4_ROM_SIG4_POS 0
#define BCM_ROM_SIG4_ROM_SIG4_NUMB 8
#define BCM_ROM_SIG4_ROM_SIG4_RES_VAL 0x00
//R
//BCM_ROM_SIG5
//-------------------
#define BCM_ROM_SIG5 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG5_OFFSET)
#define BCM_ROM_SIG5_RESERVED_POS 8
#define BCM_ROM_SIG5_RESERVED_NUMB 24
#define BCM_ROM_SIG5_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG5_ROM_SIG5_POS 0
#define BCM_ROM_SIG5_ROM_SIG5_NUMB 8
#define BCM_ROM_SIG5_ROM_SIG5_RES_VAL 0x00
//R
//BCM_ROM_SIG6
//-------------------
#define BCM_ROM_SIG6 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG6_OFFSET)
#define BCM_ROM_SIG6_RESERVED_POS 8
#define BCM_ROM_SIG6_RESERVED_NUMB 24
#define BCM_ROM_SIG6_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG6_ROM_SIG6_POS 0
#define BCM_ROM_SIG6_ROM_SIG6_NUMB 8
#define BCM_ROM_SIG6_ROM_SIG6_RES_VAL 0x00
//R
//BCM_ROM_SIG7
//-------------------
#define BCM_ROM_SIG7 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG7_OFFSET)
#define BCM_ROM_SIG7_RESERVED_POS 8
#define BCM_ROM_SIG7_RESERVED_NUMB 24
#define BCM_ROM_SIG7_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG7_ROM_SIG7_POS 0
#define BCM_ROM_SIG7_ROM_SIG7_NUMB 8
#define BCM_ROM_SIG7_ROM_SIG7_RES_VAL 0x00
//R
//BCM_ROM_SIG8
//-------------------
#define BCM_ROM_SIG8 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG8_OFFSET)
#define BCM_ROM_SIG8_RESERVED_POS 8
#define BCM_ROM_SIG8_RESERVED_NUMB 24
#define BCM_ROM_SIG8_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG8_ROM_SIG8_POS 0
#define BCM_ROM_SIG8_ROM_SIG8_NUMB 8
#define BCM_ROM_SIG8_ROM_SIG8_RES_VAL 0x00
//R
//BCM_ROM_SIG9
//-------------------
#define BCM_ROM_SIG9 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG9_OFFSET)
#define BCM_ROM_SIG9_RESERVED_POS 8
#define BCM_ROM_SIG9_RESERVED_NUMB 24
#define BCM_ROM_SIG9_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG9_ROM_SIG9_POS 0
#define BCM_ROM_SIG9_ROM_SIG9_NUMB 8
#define BCM_ROM_SIG9_ROM_SIG9_RES_VAL 0x00
//R
//BCM_ROM_SIG10
//-------------------
#define BCM_ROM_SIG10 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG10_OFFSET)
#define BCM_ROM_SIG10_RESERVED_POS 8
#define BCM_ROM_SIG10_RESERVED_NUMB 24
#define BCM_ROM_SIG10_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG10_RESERVED_POS 8
#define BCM_ROM_SIG10_RESERVED_NUMB 24
#define BCM_ROM_SIG10_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG10_ROM_SIG10_POS 0
#define BCM_ROM_SIG10_ROM_SIG10_NUMB 8
#define BCM_ROM_SIG10_ROM_SIG10_RES_VAL 0x00
//R
//BCM_ROM_SIG11
//-------------------
#define BCM_ROM_SIG11 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG11_OFFSET)
#define BCM_ROM_SIG11_RESERVED_POS 8
#define BCM_ROM_SIG11_RESERVED_NUMB 24
#define BCM_ROM_SIG11_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG11_ROM_SIG11_POS 0
#define BCM_ROM_SIG11_ROM_SIG11_NUMB 8
#define BCM_ROM_SIG11_ROM_SIG11_RES_VAL 0x00
//R
//BCM_BIST0_CTRL_STS
//-------------------
#define BCM_BIST0_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_BIST0_CTRL_STS_OFFSET)
#define BCM_BIST0_CTRL_STS_RESERVED_POS 4
#define BCM_BIST0_CTRL_STS_RESERVED_NUMB 28
#define BCM_BIST0_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_BIST0_CTRL_STS_DONE_0_POS 3
#define BCM_BIST0_CTRL_STS_DONE_0_NUMB 1
#define BCM_BIST0_CTRL_STS_DONE_0_RES_VAL 0x0
//R
#define BCM_BIST0_CTRL_STS_FAIL_0_POS 2
#define BCM_BIST0_CTRL_STS_FAIL_0_NUMB 1
#define BCM_BIST0_CTRL_STS_FAIL_0_RES_VAL 0x0
//R
#define BCM_BIST0_CTRL_STS_BM_0_POS 1
#define BCM_BIST0_CTRL_STS_BM_0_NUMB 1
#define BCM_BIST0_CTRL_STS_BM_0_RES_VAL 0x0
//R/W
#define BCM_BIST0_CTRL_STS_EN_0_POS 0
#define BCM_BIST0_CTRL_STS_EN_0_NUMB 1
#define BCM_BIST0_CTRL_STS_EN_0_RES_VAL 0x0
//R/W
//BCM_BIST1_CTRL_STS
//-------------------
#define BCM_BIST1_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_BIST1_CTRL_STS_OFFSET)
#define BCM_BIST1_CTRL_STS_RESERVED_POS 4
#define BCM_BIST1_CTRL_STS_RESERVED_NUMB 28
#define BCM_BIST1_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_BIST1_CTRL_STS_DONE_1_POS 3
#define BCM_BIST1_CTRL_STS_DONE_1_NUMB 1
#define BCM_BIST1_CTRL_STS_DONE_1_RES_VAL 0x0
//R
#define BCM_BIST1_CTRL_STS_FAIL_1_POS 2
#define BCM_BIST1_CTRL_STS_FAIL_1_NUMB 1
#define BCM_BIST1_CTRL_STS_FAIL_1_RES_VAL 0x0
//R
#define BCM_BIST1_CTRL_STS_BM_1_POS 1
#define BCM_BIST1_CTRL_STS_BM_1_NUMB 1
#define BCM_BIST1_CTRL_STS_BM_1_RES_VAL 0x0
//R/W
#define BCM_BIST1_CTRL_STS_EN_1_POS 0
#define BCM_BIST1_CTRL_STS_EN_1_NUMB 1
#define BCM_BIST1_CTRL_STS_EN_1_RES_VAL 0x0
//R/W
//BCM_BIST2_CTRL_STS
//-------------------
#define BCM_BIST2_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_BIST2_CTRL_STS_OFFSET)
#define BCM_BIST2_CTRL_STS_RESERVED_POS 4
#define BCM_BIST2_CTRL_STS_RESERVED_NUMB 28
#define BCM_BIST2_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_BIST2_CTRL_STS_DONE_2_POS 3
#define BCM_BIST2_CTRL_STS_DONE_2_NUMB 1
#define BCM_BIST2_CTRL_STS_DONE_2_RES_VAL 0x0
//R
#define BCM_BIST2_CTRL_STS_FAIL_2_POS 2
#define BCM_BIST2_CTRL_STS_FAIL_2_NUMB 1
#define BCM_BIST2_CTRL_STS_FAIL_2_RES_VAL 0x0
//R
#define BCM_BIST2_CTRL_STS_BM_2_POS 1
#define BCM_BIST2_CTRL_STS_BM_2_NUMB 1
#define BCM_BIST2_CTRL_STS_BM_2_RES_VAL 0x0
//R/W
#define BCM_BIST2_CTRL_STS_EN_2_POS 0
#define BCM_BIST2_CTRL_STS_EN_2_NUMB 1
#define BCM_BIST2_CTRL_STS_EN_2_RES_VAL 0x0
//R/W
//BCM_BIST3_CTRL_STS
//-------------------
#define BCM_BIST3_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_BIST3_CTRL_STS_OFFSET)
#define BCM_BIST3_CTRL_STS_RESERVED_POS 4
#define BCM_BIST3_CTRL_STS_RESERVED_NUMB 28
#define BCM_BIST3_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_BIST3_CTRL_STS_DONE_3_POS 3
#define BCM_BIST3_CTRL_STS_DONE_3_NUMB 1
#define BCM_BIST3_CTRL_STS_DONE_3_RES_VAL 0x0
//R
#define BCM_BIST3_CTRL_STS_FAIL_3_POS 2
#define BCM_BIST3_CTRL_STS_FAIL_3_NUMB 1
#define BCM_BIST3_CTRL_STS_FAIL_3_RES_VAL 0x0
//R
#define BCM_BIST3_CTRL_STS_BM_3_POS 1
#define BCM_BIST3_CTRL_STS_BM_3_NUMB 1
#define BCM_BIST3_CTRL_STS_BM_3_RES_VAL 0x0
//R/W
#define BCM_BIST3_CTRL_STS_EN_3_POS 0
#define BCM_BIST3_CTRL_STS_EN_3_NUMB 1
#define BCM_BIST3_CTRL_STS_EN_3_RES_VAL 0x0
//R/W
//BCM_BIST4_CTRL_STS
//-------------------
#define BCM_BIST4_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_BIST4_CTRL_STS_OFFSET)
#define BCM_BIST4_CTRL_STS_RESERVED_POS 4
#define BCM_BIST4_CTRL_STS_RESERVED_NUMB 28
#define BCM_BIST4_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_BIST4_CTRL_STS_DONE_4_POS 3
#define BCM_BIST4_CTRL_STS_DONE_4_NUMB 1
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