📄 bcm.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :bcm.h
//
// Date of Module Modification:2/18/04
// Date of Generation :2/18/04
//
//
//========================================================================
#include "mapping.h"
#ifndef _BCM__H
#define _BCM__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define BCM_DEVICE_ID_OFFSET 0x00
#define BCM_IDDQ_DATA_LOG_REG_OFFSET 0x04
#define BCM_GLOB_CTRL_STS_OFFSET 0x08
#define BCM_ROM0_CTRL_STS_OFFSET 0x0C
#define BCM_ROM1_CTRL_STS_OFFSET 0x10
#define BCM_ROM_SIG0_OFFSET 0x14
#define BCM_ROM_SIG1_OFFSET 0x18
#define BCM_ROM_SIG2_OFFSET 0x1C
#define BCM_ROM_SIG3_OFFSET 0x20
#define BCM_ROM_SIG4_OFFSET 0x24
#define BCM_ROM_SIG5_OFFSET 0x28
#define BCM_ROM_SIG6_OFFSET 0x2C
#define BCM_ROM_SIG7_OFFSET 0x30
#define BCM_ROM_SIG8_OFFSET 0x34
#define BCM_ROM_SIG9_OFFSET 0x38
#define BCM_ROM_SIG10_OFFSET 0x3C
#define BCM_ROM_SIG11_OFFSET 0x40
#define BCM_BIST0_CTRL_STS_OFFSET 0x44
#define BCM_BIST1_CTRL_STS_OFFSET 0x48
#define BCM_BIST2_CTRL_STS_OFFSET 0x4C
#define BCM_BIST3_CTRL_STS_OFFSET 0x50
#define BCM_BIST4_CTRL_STS_OFFSET 0x54
#define BCM_BIST5_CTRL_STS_OFFSET 0x58
#define BCM_BIST6_CTRL_STS_OFFSET 0x5C
#define BCM_BIST7_CTRL_STS_OFFSET 0x60
#define BCM_BIST8_CTRL_STS_OFFSET 0x64
#define BCM_BIST9_CTRL_STS_OFFSET 0x68
#define BCM_BIST10_CTRL_STS_OFFSET 0x6C
#define BCM_BIST11_CTRL_STS_OFFSET 0x70
#define BCM_BIST12_CTRL_STS_OFFSET 0x74
//BCM_DEVICE_ID
//-------------------
#define BCM_DEVICE_ID REG32(BCM_BASE_ADDR_ARM+BCM_DEVICE_ID_OFFSET)
#define BCM_DEVICE_ID_RESERVED_POS 8
#define BCM_DEVICE_ID_RESERVED_NUMB 24
#define BCM_DEVICE_ID_RESERVED_RES_VAL 0x0
//R
#define BCM_DEVICE_ID_DEVICE_ID_POS 0
#define BCM_DEVICE_ID_DEVICE_ID_NUMB 8
#define BCM_DEVICE_ID_DEVICE_ID_RES_VAL 0x10
//R
//BCM_IDDQ_DATA_LOG_REG
//-------------------
#define BCM_IDDQ_DATA_LOG_REG REG32(BCM_BASE_ADDR_ARM+BCM_IDDQ_DATA_LOG_REG_OFFSET)
#define BCM_IDDQ_DATA_LOG_REG_RESERVED_POS 8
#define BCM_IDDQ_DATA_LOG_REG_RESERVED_NUMB 24
#define BCM_IDDQ_DATA_LOG_REG_RESERVED_RES_VAL 0x0
//R
#define BCM_IDDQ_DATA_LOG_REG_RATIO_EN_POS 5
#define BCM_IDDQ_DATA_LOG_REG_RATIO_EN_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_RATIO_EN_RES_VAL 0x0
//R/W
#define BCM_IDDQ_DATA_LOG_REG_BIST_RESUME_POS 4
#define BCM_IDDQ_DATA_LOG_REG_BIST_RESUME_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_BIST_RESUME_RES_VAL 0x0
//R/W
#define BCM_IDDQ_DATA_LOG_REG_RST_POS 3
#define BCM_IDDQ_DATA_LOG_REG_RST_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_RST_RES_VAL 0x0
//R/W
#define BCM_IDDQ_DATA_LOG_REG_DEBUG_POS 2
#define BCM_IDDQ_DATA_LOG_REG_DEBUG_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_DEBUG_RES_VAL 0x0
//R/W
#define BCM_IDDQ_DATA_LOG_REG_BIST_HOLD_POS 1
#define BCM_IDDQ_DATA_LOG_REG_BIST_HOLD_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_BIST_HOLD_RES_VAL 0x0
//R/W
#define BCM_IDDQ_DATA_LOG_REG_OE_POS 0
#define BCM_IDDQ_DATA_LOG_REG_OE_NUMB 1
#define BCM_IDDQ_DATA_LOG_REG_OE_RES_VAL 0x0
//R/W
//BCM_GLOB_CTRL_STS
//-------------------
#define BCM_GLOB_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_GLOB_CTRL_STS_OFFSET)
#define BCM_GLOB_CTRL_STS_RESERVED_POS 8
#define BCM_GLOB_CTRL_STS_RESERVED_NUMB 24
#define BCM_GLOB_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_GLOB_CTRL_STS_DONE_A_POS 4
#define BCM_GLOB_CTRL_STS_DONE_A_NUMB 1
#define BCM_GLOB_CTRL_STS_DONE_A_RES_VAL 0x0
//R
#define BCM_GLOB_CTRL_STS_FAIL_A_POS 3
#define BCM_GLOB_CTRL_STS_FAIL_A_NUMB 1
#define BCM_GLOB_CTRL_STS_FAIL_A_RES_VAL 0x0
//R
#define BCM_GLOB_CTRL_STS_BM_A_POS 1
#define BCM_GLOB_CTRL_STS_BM_A_NUMB 1
#define BCM_GLOB_CTRL_STS_BM_A_RES_VAL 0x0
//R/W
#define BCM_GLOB_CTRL_STS_EN_A_POS 0
#define BCM_GLOB_CTRL_STS_EN_A_NUMB 1
#define BCM_GLOB_CTRL_STS_EN_A_RES_VAL 0x0
//R/W
//BCM_ROM0_CTRL_STS
//-------------------
#define BCM_ROM0_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_ROM0_CTRL_STS_OFFSET)
#define BCM_ROM0_CTRL_STS_RESERVED_POS 8
#define BCM_ROM0_CTRL_STS_RESERVED_NUMB 24
#define BCM_ROM0_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM0_CTRL_STS_DONE_0_POS 3
#define BCM_ROM0_CTRL_STS_DONE_0_NUMB 1
#define BCM_ROM0_CTRL_STS_DONE_0_RES_VAL 0x0
//R
#define BCM_ROM0_CTRL_STS_RESERVED_POS 2
#define BCM_ROM0_CTRL_STS_RESERVED_NUMB 1
#define BCM_ROM0_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM0_CTRL_STS_BM_0_POS 1
#define BCM_ROM0_CTRL_STS_BM_0_NUMB 1
#define BCM_ROM0_CTRL_STS_BM_0_RES_VAL 0x0
//R/W
#define BCM_ROM0_CTRL_STS_EN_0_POS 0
#define BCM_ROM0_CTRL_STS_EN_0_NUMB 1
#define BCM_ROM0_CTRL_STS_EN_0_RES_VAL 0x0
//R/W
//BCM_ROM1_CTRL_STS
//-------------------
#define BCM_ROM1_CTRL_STS REG32(BCM_BASE_ADDR_ARM+BCM_ROM1_CTRL_STS_OFFSET)
#define BCM_ROM1_CTRL_STS_RESERVED_POS 8
#define BCM_ROM1_CTRL_STS_RESERVED_NUMB 24
#define BCM_ROM1_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM1_CTRL_STS_DONE_1_POS 3
#define BCM_ROM1_CTRL_STS_DONE_1_NUMB 1
#define BCM_ROM1_CTRL_STS_DONE_1_RES_VAL 0x0
//R
#define BCM_ROM1_CTRL_STS_RESERVED_POS 2
#define BCM_ROM1_CTRL_STS_RESERVED_NUMB 1
#define BCM_ROM1_CTRL_STS_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM1_CTRL_STS_BM_1_POS 1
#define BCM_ROM1_CTRL_STS_BM_1_NUMB 1
#define BCM_ROM1_CTRL_STS_BM_1_RES_VAL 0x0
//R/W
#define BCM_ROM1_CTRL_STS_EN_1_POS 0
#define BCM_ROM1_CTRL_STS_EN_1_NUMB 1
#define BCM_ROM1_CTRL_STS_EN_1_RES_VAL 0x0
//R/W
//BCM_ROM_SIG0
//-------------------
#define BCM_ROM_SIG0 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG0_OFFSET)
#define BCM_ROM_SIG0_RESERVED_POS 8
#define BCM_ROM_SIG0_RESERVED_NUMB 24
#define BCM_ROM_SIG0_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG0_ROM_SIG0_POS 0
#define BCM_ROM_SIG0_ROM_SIG0_NUMB 8
#define BCM_ROM_SIG0_ROM_SIG0_RES_VAL 0x00
//R
//BCM_ROM_SIG1
//-------------------
#define BCM_ROM_SIG1 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG1_OFFSET)
#define BCM_ROM_SIG1_RESERVED_POS 8
#define BCM_ROM_SIG1_RESERVED_NUMB 24
#define BCM_ROM_SIG1_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG1_ROM_SIG1_POS 0
#define BCM_ROM_SIG1_ROM_SIG1_NUMB 8
#define BCM_ROM_SIG1_ROM_SIG1_RES_VAL 0x00
//R
//BCM_ROM_SIG2
//-------------------
#define BCM_ROM_SIG2 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG2_OFFSET)
#define BCM_ROM_SIG2_RESERVED_POS 8
#define BCM_ROM_SIG2_RESERVED_NUMB 24
#define BCM_ROM_SIG2_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG2_ROM_SIG2_POS 0
#define BCM_ROM_SIG2_ROM_SIG2_NUMB 8
#define BCM_ROM_SIG2_ROM_SIG2_RES_VAL 0x00
//R
//BCM_ROM_SIG3
//-------------------
#define BCM_ROM_SIG3 REG32(BCM_BASE_ADDR_ARM+BCM_ROM_SIG3_OFFSET)
#define BCM_ROM_SIG3_RESERVED_POS 8
#define BCM_ROM_SIG3_RESERVED_NUMB 24
#define BCM_ROM_SIG3_RESERVED_RES_VAL 0x0
//R
#define BCM_ROM_SIG3_ROM_SIG3_POS 0
#define BCM_ROM_SIG3_ROM_SIG3_NUMB 8
#define BCM_ROM_SIG3_ROM_SIG3_RES_VAL 0x00
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