pstxnet.dat

基于SIIGX的PCIe的Kit

NODE_NAME	U21 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'CLK_EN':;
NODE_NAME	R107 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'FPGA_CONFIG_D5'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FPGA_CONFIG_D5':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):fpga_config_d5';
NODE_NAME	U10 H30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DATA5':;
NODE_NAME	U4 44
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO/DEV_CLRN':;
NET_NAME
'HSMB_TX_D_P10'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_P10':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_p10';
NODE_NAME	U10 AB32
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX20P':;
NODE_NAME	J2 113
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '113':;
NET_NAME
'HSMA_TX_D_P6'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_TX_D_P6':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_tx_d_p6';
NODE_NAME	U10 P30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX47P':;
NODE_NAME	J1 83
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '83':;
NET_NAME
'QDRII_RUP'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):QDRII_RUP':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):qdrii_rup';
NODE_NAME	U10 N13
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'RUP4':;
NODE_NAME	R162 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'HSMB_TX_P2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_P2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_p2';
NODE_NAME	C43 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	U10 AU4
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_TX18P':;
NET_NAME
'FPGA_CONFIG_D4'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FPGA_CONFIG_D4':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):fpga_config_d4';
NODE_NAME	U10 F31
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DATA4':;
NODE_NAME	U4 83
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO57':;
NET_NAME
'HSMA_RX_D_P7'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_P7':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_p7';
NODE_NAME	U10 T38
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX30P':;
NODE_NAME	J1 90
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '90':;
NET_NAME
'HSMB_TX_D_P4'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_P4':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_p4';
NODE_NAME	U10 AB30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX21P':;
NODE_NAME	J2 71
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '71':;
NET_NAME
'HSMB_RX_P3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_RX_P3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_rx_p3';
NODE_NAME	U10 AW3
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_RX19P':;
NODE_NAME	J2 18
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '18':;
NET_NAME
'FPGA_CONFIG_D6'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FPGA_CONFIG_D6':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):fpga_config_d6';
NODE_NAME	U10 G30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DATA6':;
NODE_NAME	U4 57
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO39':;
NET_NAME
'HSMB_TX_D_N3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n3';
NODE_NAME	U10 AE33
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX13N':;
NODE_NAME	J2 67
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '67':;
NET_NAME
'HSMA_TX_D_P3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_TX_D_P3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_tx_d_p3';
NODE_NAME	U10 K30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX55P':;
NODE_NAME	J1 65
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '65':;
NET_NAME
'FLASH_WEN'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_WEN':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_wen';
NODE_NAME	U10 L27
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B3_IO26':;
NODE_NAME	U3 A5
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'WEN':;
NODE_NAME	R18 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	U4 21
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO15':;
NET_NAME
'HSMB_RX_P2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_RX_P2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_rx_p2';
NODE_NAME	U10 AU1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_RX18P':;
NODE_NAME	J2 22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '22':;
NET_NAME
'FPGA_CONFIG_D7'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FPGA_CONFIG_D7':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):fpga_config_d7';
NODE_NAME	U10 F32
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DATA7':;
NODE_NAME	U4 95
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO65':;
NET_NAME
'HSMA_TX_D_N10'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_TX_D_N10':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_tx_d_n10';
NODE_NAME	U10 L33
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX53N':;
NODE_NAME	J1 115
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '115':;
NET_NAME
'HSMB_TX_D_P2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_P2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_p2';
NODE_NAME	U10 AA27
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX26P':;
NODE_NAME	J2 59
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '59':;
NET_NAME
'HSMB_TX_N3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_N3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_n3';
NODE_NAME	C44 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	U10 AW7
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_TX19N':;
NET_NAME
'HSMB_TX_D_P3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_P3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_p3';
NODE_NAME	U10 AD33
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX13P':;
NODE_NAME	J2 65
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '65':;
NET_NAME
'HSMA_TX_D_P8'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_TX_D_P8':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_tx_d_p8';
NODE_NAME	U10 N27
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX49P':;
NODE_NAME	J1 101
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '101':;
NET_NAME
'HSMB_TX_N0'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_N0':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_n0';
NODE_NAME	C40 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	U10 AR5
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_TX16N':;
NET_NAME
'HSMB_TX_D_N2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n2';
NODE_NAME	U10 AB27
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX26N':;
NODE_NAME	J2 61
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '61':;
NET_NAME
'HSMA_RX_D_P10'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_P10':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_p10';
NODE_NAME	U10 K39
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX42P':;
NODE_NAME	J1 114
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '114':;
NET_NAME
'HSMB_RX_N3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_RX_N3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_rx_n3';
NODE_NAME	U10 AW4
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_RX19N':;
NODE_NAME	J2 20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '20':;
NET_NAME
'HSMA_RX_D_N0'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_N0':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_n0';
NODE_NAME	U10 J38
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX44N':;
NODE_NAME	J1 50
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '50':;
NET_NAME
'HSMB_TX_D_N7'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N7':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n7';
NODE_NAME	U10 AE26
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX17N':;
NODE_NAME	J2 91
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '91':;
NET_NAME
'HSMB_RX_N2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_RX_N2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_rx_n2';
NODE_NAME	U10 AU2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_RX18N':;
NODE_NAME	J2 24
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '24':;
NET_NAME
'SMA_CLK'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SMA_CLK':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sma_clk';
NODE_NAME	R114 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	J4 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS27362632@STRATIX_MEM2_7.SMA_LTI_SASF54GT_0.NORMAL(CHIPS)':
 '1':;
NODE_NAME	U21 6
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PCLKP':;
NET_NAME
'HSMA_RX_D_P8'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_P8':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_p8';
NODE_NAME	U10 U37
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX31P':;
NODE_NAME	J1 102
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '102':;
NET_NAME
'HSMB_TX_D_N5'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N5':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n5';
NODE_NAME	U10 AC25
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX23N':;
NODE_NAME	J2 79
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '79':;
NET_NAME
'HSMB_RX_P1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_RX_P1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_rx_p1';
NODE_NAME	U10 AN1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_RX17P':;
NODE_NAME	J2 26
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '26':;
NET_NAME
'HSMB_TX_D_N4'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N4':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n4';
NODE_NAME	U10 AB29
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX21N':;
NODE_NAME	J2 73
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '73':;
NET_NAME
'HSMA_RX_D_N4'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_N4':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_n4';
NODE_NAME	U10 N37
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX38N':;
NODE_NAME	J1 74
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '74':;
NET_NAME
'HSMB_TX_P3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_P3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_p3';
NODE_NAME	C45 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	U10 AW6
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NC/GXB_TX19P':;
NET_NAME
'HSMB_TX_D_N1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMB_TX_D_N1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsmb_tx_d_n1';
NODE_NAME	U10 AA26
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX27N':;
NODE_NAME	J2 55
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '55':;
NET_NAME
'HSMA_RX_D_P16'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_RX_D_P16':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_rx_d_p16';
NODE_NAME	U10 U39
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_RX29P':;
NODE_NAME	J1 150
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '150':;