pstxnet.dat

基于SIIGX的PCIe的Kit

FILE_TYPE = EXPANDEDNETLIST;
{ Using PSTWRITER 10.5.0 p001Aug-21-2006 at 16:40:33 }
NET_NAME
'HSMA_CLK_OUT_N2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_CLK_OUT_N2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_clk_out_n2';
NODE_NAME	U10 T30
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX41N':;
NODE_NAME	J1 157
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '157':;
NET_NAME
'SFPA_VCCR'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SFPA_VCCR':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sfpa_vccr';
NODE_NAME	C366 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	L4 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS19248868@TEST_CHIP_APPS_DEMO.INDUCTOR_SMD_1.NORMAL(CHIPS)':
 '2':;
NODE_NAME	J6 15
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]20_AND_CAGE.NORMAL(CHIPS)':
 'VCCR':;
NODE_NAME	C367 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'SFPA_VCCT'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SFPA_VCCT':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sfpa_vcct';
NODE_NAME	J6 16
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]20_AND_CAGE.NORMAL(CHIPS)':
 'VCCT':;
NODE_NAME	C330 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	L3 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS19248711@TEST_CHIP_APPS_DEMO.INDUCTOR_SMD_1.NORMAL(CHIPS)':
 '2':;
NET_NAME
'SFPB_MOD0_PRSNTN'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SFPB_MOD0_PRSNTN':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sfpb_mod0_prsntn';
NODE_NAME	U10 P18
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B4_IO28':;
NODE_NAME	R186 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	J7 6
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]20_AND_CAGE.NORMAL(CHIPS)':
 'MOD_DEF0':;
NET_NAME
'ENET_RX_ER'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):ENET_RX_ER':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):enet_rx_er';
NODE_NAME	U10 G24
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'NCSO':;
NODE_NAME	U1 3
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'RX_ER':;
NET_NAME
'PORSEL'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):PORSEL':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):porsel';
NODE_NAME	U10 AL10
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PORSEL':;
NODE_NAME	R165 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'SFPA_MOD0_PRSNTN'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SFPA_MOD0_PRSNTN':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sfpa_mod0_prsntn';
NODE_NAME	U10 D11
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DQS1T':;
NODE_NAME	R156 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	J6 6
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]20_AND_CAGE.NORMAL(CHIPS)':
 'MOD_DEF0':;
NET_NAME
'HSMA_D2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_D2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_d2';
NODE_NAME	U10 A22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL11_OUT0P':;
NODE_NAME	J1 43
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '43':;
NET_NAME
'SFPA_MOD1_SCL'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):SFPA_MOD1_SCL':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):sfpa_mod1_scl';
NODE_NAME	U10 N15
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B4_IO19':;
NODE_NAME	R153 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	J6 5
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]20_AND_CAGE.NORMAL(CHIPS)':
 'MOD_DEF1':;
NET_NAME
'HSMA_D1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_D1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_d1';
NODE_NAME	U10 F22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL11_FBP/OUT2P':;
NODE_NAME	J1 42
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '42':;
NET_NAME
'DDR2_CK_P2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_P2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_p2';
NODE_NAME	U10 AP20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_FBP/OUT2P':;
NODE_NAME	U2 E8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M8BP_0.NORMAL(CHIPS)':
 'CK_P':;
NODE_NAME	R106 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NODE_NAME	C96 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'HSMA_D0'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_D0':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_d0';
NODE_NAME	U10 D22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL11_OUT1P':;
NODE_NAME	J1 41
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '41':;
NET_NAME
'VCC_SEL'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):VCC_SEL':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):vcc_sel';
NODE_NAME	U10 AT34
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'VCCSEL':;
NODE_NAME	R136 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'DDR2_CK_P1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_P1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_p1';
NODE_NAME	U10 AU20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_OUT1P':;
NODE_NAME	U8 J8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_P':;
NODE_NAME	U5 J8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_P':;
NODE_NAME	R133 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'HSMA_D3'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_D3':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_d3';
NODE_NAME	U10 B22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL11_OUT0N':;
NODE_NAME	J1 44
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '44':;
NET_NAME
'N28140727'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):N28140727':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):n28140727';
NODE_NAME	R67 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R66 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R65 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R64 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R63 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R62 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R61 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R60 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R59 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	R58 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'HSMA_CLK_OUT_N1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):HSMA_CLK_OUT_N1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):hsma_clk_out_n1';
NODE_NAME	U10 Y31
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'DIFFIO_TX29N':;
NODE_NAME	J1 97
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]_060.NORMAL(CHIPS)':
 '97':;
NET_NAME
'FLASH_A20'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_A20':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_a20';
NODE_NAME	U10 AM16
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B7_IO26':;
NODE_NAME	U3 D4
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'A20':;
NODE_NAME	U4 54
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO36':;
NET_NAME
'FLASH_A23'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_A23':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_a23';
NODE_NAME	U10 AG22
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B8_IO2':;
NODE_NAME	U3 C8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'A23':;
NODE_NAME	U4 35
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO23':;
NET_NAME
'FLASH_A24'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_A24':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_a24';
NODE_NAME	U10 AN29
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B8_IO30':;
NODE_NAME	U3 F8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'A24':;
NODE_NAME	U4 12
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO/GCLK0':;
NET_NAME
'DDR2_CK_N1'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_N1':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_n1';
NODE_NAME	U10 AT20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_OUT1N':;
NODE_NAME	U8 K8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_N':;
NODE_NAME	U5 K8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_N':;
NODE_NAME	R133 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'FLASH_A22'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_A22':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_a22';
NODE_NAME	U10 AM27
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B8_IO23':;
NODE_NAME	U3 B8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'A22':;
NODE_NAME	U4 15
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO9':;
NET_NAME
'DDR2_CK_N0'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_N0':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_n0';
NODE_NAME	U10 AV19
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_OUT0N':;
NODE_NAME	U11 K8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_N':;
NODE_NAME	U13 K8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_N':;
NODE_NAME	R169 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NET_NAME
'FLASH_A21'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_A21':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_a21';
NODE_NAME	U10 AK24
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'B8_IO14':;
NODE_NAME	U3 C5
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'A21':;
NODE_NAME	U4 29
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO19':;
NET_NAME
'DDR2_CK_P0'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_P0':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_p0';
NODE_NAME	U10 AW19
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_OUT0P':;
NODE_NAME	U13 J8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_P':;
NODE_NAME	U11 J8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M16CC_0AA.NORMAL(CHIPS)':
 'CK_P':;
NODE_NAME	R169 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'FLASH_CEN'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):FLASH_CEN':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):flash_cen';
NODE_NAME	U10 C20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL5_OUT1P':;
NODE_NAME	U3 F2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):INS38224755@S2GXPCIE.S29GLXXXN_BGA_1.NORMAL(CHIPS)':
 'CEN':;
NODE_NAME	R110 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	U4 5
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]570_TQFP100_0.NORMAL(CHIPS)':
 'IO5':;
NET_NAME
'DDR2_CK_N2'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):DDR2_CK_N2':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):ddr2_ck_n2';
NODE_NAME	U10 AN20
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 'PLL6_FBN/OUT2N':;
NODE_NAME	U2 F8
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail]47H32M8BP_0.NORMAL(CHIPS)':
 'CK_N':;
NODE_NAME	R106 2
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '2':;
NODE_NAME	C97 1
 '@S2GXPCIE.SCHEMATIC1(SCH_1):[e-mail](CHIPS)':
 '1':;
NET_NAME
'N40245312'
 '@S2GXPCIE.SCHEMATIC1(SCH_1):N40245312':
 C_SIGNAL='@s2gxpcie.schematic1(sch_1):n40245312';