📄 s2gx_pcie_top.pin
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 1.8V
-- Bank 4: 1.8V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 1.8V
-- Bank 8: 1.8V
-- Bank 9: 1.8V
-- Bank 10: 1.8V
-- Bank 11: 2.5V
-- Bank 12: 2.5V
-- Bank 13: 2.5V
-- Bank 14: 2.5V
-- Bank 15: 2.5V
-- Bank 16: 2.5V
-- RREF : External reference resistor for the quad, MUST be connected to
-- GND via a 2k Ohm resistor.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- GXB_VCC* : Connect to VCCT or VCCR through a 10K resistor, to improve tolerance
-- to noise.
---------------------------------------------------------------------------------
Quartus II Version 6.0 Build 178 04/27/2006 SJ Full Version
CHIP "s2gx_pcie_top" ASSIGNED TO AN: EP2SGX90FF1508C3
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND* : A2 : gnd : : : :
GXB_VCC* : A3 : : : 1.5V : 13 :
GND* : A4 : : : : 13 :
GND* : A5 : gnd : : : :
GXB_VCC* : A6 : : : 1.5V : 13 :
GND* : A7 : : : : 13 :
GND* : A8 : gnd : : : :
qdrii_bwsn[0] : A9 : output : 1.8-V HSTL Class I : : 4 : Y
qdrii_bwsn[3] : A10 : output : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[12] : A11 : input : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[5] : A12 : input : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[15] : A13 : input : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[8] : A14 : input : 1.8-V HSTL Class I : : 4 : Y
flash_d[15] : A15 : bidir : 1.8 V : : 4 : Y
qdrii_q[25] : A16 : input : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[23] : A17 : input : 1.8-V HSTL Class I : : 4 : Y
qdrii_q[22] : A18 : input : 1.8-V HSTL Class I : : 4 : Y
RESERVED_INPUT : A19 : : : : 9 :
clk1_p : A20 : input : LVDS : : 4 : Y
clk1_p(n) : A21 : input : LVDS : : 4 : N
hsma_d[2] : A22 : bidir : 2.5 V : : 11 : Y
qdrii_d[12] : A23 : output : 1.8-V HSTL Class I : : 3 : Y
flash_d[8] : A24 : bidir : 1.8 V : : 3 : Y
flash_oen : A25 : output : 1.8 V : : 3 : Y
flash_d[4] : A26 : bidir : 1.8 V : : 3 : Y
flash_d[9] : A27 : bidir : 1.8 V : : 3 : Y
enet_mdc : A28 : output : 1.8 V : : 3 : Y
enet_intn : A29 : input : 1.8 V : : 3 : Y
qdrii_d[23] : A30 : output : 1.8-V HSTL Class I : : 3 : Y
qdrii_d[30] : A31 : output : 1.8-V HSTL Class I : : 3 : Y
qdrii_d[22] : A32 : output : 1.8-V HSTL Class I : : 3 : Y
qdrii_d[20] : A33 : output : 1.8-V HSTL Class I : : 3 : Y
flash_resetn : A34 : output : 1.8 V : : 3 : Y
enet_rxd[1] : A35 : input : 1.8 V : : 3 : Y
qdrii_d[32] : A36 : output : 1.8-V HSTL Class I : : 3 : Y
enet_tx_en : A37 : output : 1.8 V : : 3 : Y
GND : A38 : gnd : : : :
GXB_VCC* : AA1 : : : 1.5V : 15 :
GND* : AA2 : : : : 15 :
GND* : AA3 : gnd : : : :
GXB_VCC* : AA4 : : : 1.5V : 15 :
GND* : AA5 : : : : 15 :
GND* : AA6 : gnd : : : :
GND* : AA7 : gnd : : : :
GND* : AA8 : gnd : : : :
VCCL : AA9 : power : : 1.2V : :
GND* : AA10 : gnd : : : :
GND* : AA11 : gnd : : : :
GND* : AA12 : gnd : : : :
GND* : AA13 : gnd : : : :
GND : AA14 : gnd : : : :
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