hsmc_spi42tx.v

基于SIIGX的PCIe的Kit

// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_tx 

// ============================================================
// File Name: hsmc_spi42tx.v
// Megafunction Name(s):
// 			altlvds_tx
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SP 0.10 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hsmc_spi42tx (
	tx_in,
	tx_inclock,
	tx_out,
	tx_outclock);

	input	[135:0]  tx_in;
	input	  tx_inclock;
	output	[16:0]  tx_out;
	output	  tx_outclock;

	wire [16:0] sub_wire0;
	wire  sub_wire1;
	wire [16:0] tx_out = sub_wire0[16:0];
	wire  tx_outclock = sub_wire1;

	altlvds_tx	altlvds_tx_component (
				.tx_in (tx_in),
				.tx_inclock (tx_inclock),
				.tx_out (sub_wire0),
				.tx_outclock (sub_wire1)
				// synopsys translate_off
				,
				.tx_locked (),
				.pll_areset (),
				.tx_enable (),
				.tx_pll_enable (),
				.tx_coreclock (),
				.sync_inclock ()
				// synopsys translate_on
				);
	defparam
		altlvds_tx_component.common_rx_tx_pll = "OFF",
		altlvds_tx_component.deserialization_factor = 8,
		altlvds_tx_component.implement_in_les = "OFF",
		altlvds_tx_component.inclock_data_alignment = "EDGE_ALIGNED",
		altlvds_tx_component.inclock_period = 10000,
		altlvds_tx_component.intended_device_family = "Stratix II GX",
		altlvds_tx_component.lpm_type = "altlvds_tx",
		altlvds_tx_component.number_of_channels = 17,
		altlvds_tx_component.outclock_alignment = "EDGE_ALIGNED",
		altlvds_tx_component.outclock_divide_by = 4,
		altlvds_tx_component.outclock_resource = "AUTO",
		altlvds_tx_component.output_data_rate = 800,
		altlvds_tx_component.registered_input = "TX_CORECLK",
		altlvds_tx_component.use_external_pll = "OFF";


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Clock_Choices STRING "TX_CORECLK"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "800"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "8"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: Input_Clock_alignment STRING "EDGE_ALIGNED"
// Retrieval info: PRIVATE: Int_Device STRING "Stratix II GX"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "17"
// Retrieval info: PRIVATE: Outclock_Divide_By NUMERIC "4"
// Retrieval info: PRIVATE: Output_Clock_alignment STRING "EDGE_ALIGNED"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "100.00"
// Retrieval info: PRIVATE: PLL_Period STRING "10.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
// Retrieval info: PRIVATE: Use_CoreClock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "8"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "17"
// Retrieval info: CONSTANT: OUTCLOCK_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: OUTCLOCK_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "800"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CORECLK"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: USED_PORT: tx_in 0 0 136 0 INPUT NODEFVAL tx_in[135..0]
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT GND tx_inclock
// Retrieval info: USED_PORT: tx_out 0 0 17 0 OUTPUT NODEFVAL tx_out[16..0]
// Retrieval info: USED_PORT: tx_outclock 0 0 0 0 OUTPUT NODEFVAL tx_outclock
// Retrieval info: CONNECT: @tx_in 0 0 136 0 tx_in 0 0 136 0
// Retrieval info: CONNECT: tx_out 0 0 17 0 @tx_out 0 0 17 0
// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
// Retrieval info: CONNECT: tx_outclock 0 0 0 0 @tx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hsmc_spi42tx_bb.v TRUE