📄 s2gx_pcie_top.map.rpt
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Analysis & Synthesis report for s2gx_pcie_top
Mon Jul 24 12:02:17 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+--------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 24 12:02:17 2006 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; s2gx_pcie_top ;
; Top-level Entity Name ; s2gx_pcie_top ;
; Family ; Stratix II GX ;
; Total ALUTs ; 0 ;
; Total registers ; 0 ;
; Total pins ; 444 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total GXB Receiver Channels ; 0 ;
; Total GXB Transmitter Channels ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+--------------------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2SGX90FF1508C3 ; ;
; Top-level entity name ; s2gx_pcie_top ; s2gx_pcie_top ;
; Family name ; Stratix II GX ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; Unlimited ; Unlimited ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; s2gx_pcie_top.v ; yes ; User Verilog HDL File ; C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/golden_top/s2gx_pcie_top.v ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------------------+---------------+
; Resource ; Usage ;
+--------------------------------------------+---------------+
; Estimated Total ALUTs ; 0 ;
; Total combinational functions ; 0 ;
; ALUT usage by number of inputs ; ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 0 ;
; -- <=3 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ALUTs by mode ; ;
; -- normal mode ; 0 ;
; -- extended LUT mode ; 0 ;
; -- arithmetic mode ; 0 ;
; -- shared arithmetic mode ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 444 ;
; Maximum fan-out node ; user_dipsw[0] ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 8 ;
; Average fan-out ; 0.02 ;
+--------------------------------------------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
; |s2gx_pcie_top ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 444 ; 0 ; |s2gx_pcie_top ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/golden_top/s2gx_pcie_top.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Jul 24 12:02:15 2006
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off s2gx_pcie_top -c s2gx_pcie_top
Info: Found 1 design units, including 1 entities, in source file s2gx_pcie_top.v
Info: Found entity 1: s2gx_pcie_top
Info: Elaborating entity "s2gx_pcie_top" for the top level hierarchy
Warning (10034): Output port "ddr2_a[14]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[13]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[12]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[11]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[10]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[9]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[8]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[7]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[6]" at s2gx_pcie_top.v(56) has no driver
Warning (10034): Output port "ddr2_a[5]" at s2gx_pcie_top.v(56) has no driver
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