lvds_tx_b8a1.tdf

基于SIIGX的PCIe的Kit

--altlvds_tx COMMON_RX_TX_PLL="OFF" DESERIALIZATION_FACTOR=8 DEVICE_FAMILY="Stratix II GX" ENABLE_CLK_LATENCY="OFF" IMPLEMENT_IN_LES="OFF" INCLOCK_DATA_ALIGNMENT="EDGE_ALIGNED" INCLOCK_PERIOD=10000 NUMBER_OF_CHANNELS=17 OUTCLOCK_ALIGNMENT="EDGE_ALIGNED" OUTCLOCK_DIVIDE_BY=4 OUTCLOCK_RESOURCE="AUTO" OUTPUT_DATA_RATE=800 REGISTERED_INPUT="TX_CORECLK" USE_EXTERNAL_PLL="OFF" tx_in tx_inclock tx_out tx_outclock CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 6.0 cbx_altddio_in 2006:01:09:10:51:42:SJ cbx_altddio_out 2006:03:03:09:14:02:SJ cbx_altlvds_rx 2006:03:22:16:46:44:SJ cbx_altsyncram 2006:03:17:17:38:48:SJ cbx_cyclone 2006:01:09:11:15:06:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:14:18:11:20:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_lpm_shiftreg 2006:01:09:11:26:32:SJ cbx_mgl 2006:03:21:17:14:24:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION stratixiigx_clkctrl (clkselect[1..0], ena, inclk[3..0])
WITH ( 	clock_type) 
RETURNS ( outclk);
FUNCTION stratixiigx_lvds_transmitter (clk0, datain[CHANNEL_WIDTH-1..0], enable0, postdpaserialdatain, serialdatain)
WITH ( 	BYPASS_SERIALIZER,	CHANNEL_WIDTH,	DIFFERENTIAL_DRIVE,	INVERT_CLOCK,	PREEMPHASIS_SETTING,	USE_FALLING_CLOCK_EDGE,	USE_POST_DPA_SERIAL_DATA_INPUT,	USE_SERIAL_DATA_INPUT,	VOD_SETTING) 
RETURNS ( dataout, serialfdbkout);
FUNCTION stratixiigx_pll (areset, clkswitch, ena, fbin, inclk[1..0], pfdena, scanclk, scandata, scanread, scanwrite, testin[3..0])
WITH ( 	BANDWIDTH,	BANDWIDTH_TYPE,	C0_HIGH,	C0_INITIAL,	C0_LOW,	C0_MODE,	C0_PH,	C0_TEST_SOURCE,	C1_HIGH,	C1_INITIAL,	C1_LOW,	C1_MODE,	C1_PH,	C1_TEST_SOURCE,	C1_USE_CASC_IN,	C2_HIGH,	C2_INITIAL,	C2_LOW,	C2_MODE,	C2_PH,	C2_TEST_SOURCE,	C2_USE_CASC_IN,	C3_HIGH,	C3_INITIAL,	C3_LOW,	C3_MODE,	C3_PH,	C3_TEST_SOURCE,	C3_USE_CASC_IN,	C4_HIGH,	C4_INITIAL,	C4_LOW,	C4_MODE,	C4_PH,	C4_TEST_SOURCE,	C4_USE_CASC_IN,	C5_HIGH,	C5_INITIAL,	C5_LOW,	C5_MODE,	C5_PH,	C5_TEST_SOURCE,	C5_USE_CASC_IN,	CHARGE_PUMP_CURRENT,	CLK0_COUNTER,	CLK0_DIVIDE_BY,	CLK0_DUTY_CYCLE,	CLK0_MULTIPLY_BY,	CLK0_PHASE_SHIFT,	CLK1_COUNTER,	CLK1_DIVIDE_BY,	CLK1_DUTY_CYCLE,	CLK1_MULTIPLY_BY,	CLK1_PHASE_SHIFT,	CLK2_COUNTER,	CLK2_DIVIDE_BY,	CLK2_DUTY_CYCLE,	CLK2_MULTIPLY_BY,	CLK2_PHASE_SHIFT,	CLK3_COUNTER,	CLK3_DIVIDE_BY,	CLK3_DUTY_CYCLE,	CLK3_MULTIPLY_BY,	CLK3_PHASE_SHIFT,	CLK4_COUNTER,	CLK4_DIVIDE_BY,	CLK4_DUTY_CYCLE,	CLK4_MULTIPLY_BY,	CLK4_PHASE_SHIFT,	CLK5_COUNTER,	CLK5_DIVIDE_BY,	CLK5_DUTY_CYCLE,	CLK5_MULTIPLY_BY,	CLK5_PHASE_SHIFT,	COMPENSATE_CLOCK,	DOWN_SPREAD,	ENABLE0_COUNTER,	ENABLE1_COUNTER,	ENABLE_SWITCH_OVER_COUNTER,	FEEDBACK_SOURCE,	GATE_LOCK_COUNTER,	GATE_LOCK_SIGNAL,	INCLK0_INPUT_FREQUENCY,	INCLK1_INPUT_FREQUENCY,	INVALID_LOCK_MULTIPLIER,	LOCK_HIGH,	LOCK_LOW,	LOOP_FILTER_C,	LOOP_FILTER_R,	M,	M2,	M_INITIAL,	M_PH,	N,	N2,	OPERATION_MODE,	PFD_MAX,	PFD_MIN,	PLL_TYPE,	QUALIFY_CONF_DONE,	SCLKOUT0_PHASE_SHIFT,	SCLKOUT1_PHASE_SHIFT,	SPREAD_FREQUENCY,	SS,	SWITCH_OVER_COUNTER,	SWITCH_OVER_ON_GATED_LOCK,	SWITCH_OVER_ON_LOSSCLK,	SWITCH_OVER_TYPE,	TEST_FEEDBACK_COMP_DELAY_CHAIN_BITS,	TEST_INPUT_COMP_DELAY_CHAIN_BITS,	VALID_LOCK_MULTIPLIER,	VCO_CENTER,	VCO_DIVIDE_BY,	VCO_MAX,	VCO_MIN,	VCO_MULTIPLY_BY,	VCO_POST_SCALE) 
RETURNS ( activeclock, clk[5..0], clkbad[1..0], clkloss, enable0, enable1, locked, scandataout, scandone, sclkout[1..0], testdownout, testupout);

--synthesis_resources = clkctrl 1 reg 136 stratixiigx_lvds_transmitter 18 stratixiigx_pll 1 
OPTIONS ALTERA_INTERNAL_OPTION = "{-to pll} AUTO_MERGE_PLLS=OFF;{ -from ""txreg*"" -to ""tx*"" }MULTICYCLE=7;{ -from ""txreg*"" -to ""tx*"" }MULTICYCLE_HOLD=8";

SUBDESIGN lvds_tx_b8a1
( 
	tx_in[135..0]	:	input;
	tx_inclock	:	input;
	tx_out[16..0]	:	output;
	tx_outclock	:	output;
) 
VARIABLE 
	txreg[135..0] : dffe;
	coreclk_buf : stratixiigx_clkctrl
		WITH (
			clock_type = "AUTO"
		);
	outclock_tx : stratixiigx_lvds_transmitter
		WITH (
			BYPASS_SERIALIZER = "false",
			CHANNEL_WIDTH = 8,
			INVERT_CLOCK = "false",
			USE_FALLING_CLOCK_EDGE = "false"
		);
	tx[16..0] : stratixiigx_lvds_transmitter
		WITH (
			CHANNEL_WIDTH = 8
		);
	pll : stratixiigx_pll
		WITH (
			CLK0_DIVIDE_BY = 8,
			CLK0_MULTIPLY_BY = 8,
			CLK0_PHASE_SHIFT = "-625",
			COMPENSATE_CLOCK = "lvdsclk",
			INCLK0_INPUT_FREQUENCY = 10000,
			OPERATION_MODE = "normal",
			PLL_TYPE = "fast",
			SCLKOUT0_PHASE_SHIFT = "-625",
			VCO_DIVIDE_BY = 1,
			VCO_MULTIPLY_BY = 8
		);
	pll_areset	: NODE;
	tx_pll_enable	: NODE;

BEGIN 
	txreg[].CLK = coreclk_buf.outclk;
	txreg[].D = tx_in[];
	coreclk_buf.clkselect[] = B"00";
	coreclk_buf.ena = B"1";
	coreclk_buf.inclk[] = ( B"000", pll.clk[0..0]);
	outclock_tx.clk0 = pll.sclkout[0..0];
	outclock_tx.datain[] = B"11001100";
	outclock_tx.enable0 = pll.enable0;
	tx[].clk0 = pll.sclkout[0..0];
	tx[].datain[] = txreg[].Q;
	tx[].enable0 = pll.enable0;
	pll.areset = pll_areset;
	pll.ena = tx_pll_enable;
	pll.inclk[] = ( GND, tx_inclock);
	pll_areset = GND;
	tx_out[] = tx[].dataout;
	tx_outclock = outclock_tx.dataout;
	tx_pll_enable = VCC;
END;
--VALID FILE