s2gx_pcie_top.vho

基于SIIGX的PCIe的Kit

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "07/26/2007 14:43:14"

-- 
-- Device: Altera EP2SGX90FF1508C3 Package FBGA1508
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, stratixiigx;
USE IEEE.std_logic_1164.all;
USE stratixiigx.stratixiigx_components.all;

ENTITY 	s2gx_pcie_top IS
    PORT (
	clk1_p : IN std_logic;
	clk2_p : IN std_logic;
	tsense_smb_data : INOUT std_logic;
	tsense_smb_clk : IN std_logic;
	alertn : IN std_logic;
	ddr2_a : OUT std_logic_vector(14 DOWNTO 0);
	ddr2_ba : OUT std_logic_vector(2 DOWNTO 0);
	ddr2_dq : INOUT std_logic_vector(71 DOWNTO 0);
	ddr2_dqs : INOUT std_logic_vector(8 DOWNTO 0);
	ddr2_dm : OUT std_logic_vector(8 DOWNTO 0);
	ddr2_wen : OUT std_logic;
	ddr2_rasn : OUT std_logic;
	ddr2_casn : OUT std_logic;
	ddr2_ck_p : OUT std_logic_vector(2 DOWNTO 0);
	ddr2_ck_n : OUT std_logic_vector(2 DOWNTO 0);
	ddr2_cke : OUT std_logic;
	ddr2_csn : OUT std_logic;
	ddr2_odt : OUT std_logic;
	ddr2_sync_clk_out : OUT std_logic;
	ddr2_sync_clk_in : IN std_logic;
	qdrii_a : OUT std_logic_vector(18 DOWNTO 0);
	qdrii_d : OUT std_logic_vector(35 DOWNTO 0);
	qdrii_q : IN std_logic_vector(35 DOWNTO 0);
	qdrii_rpsn : OUT std_logic;
	qdrii_wpsn : OUT std_logic;
	qdrii_bwsn : OUT std_logic_vector(3 DOWNTO 0);
	qdrii_k_p : OUT std_logic;
	qdrii_k_n : OUT std_logic;
	qdrii_cq_p : IN std_logic;
	qdrii_cq_n : IN std_logic;
	enet_gtx_clk : OUT std_logic;
	enet_tx_clk : IN std_logic;
	enet_tx_er : OUT std_logic;
	enet_tx_en : OUT std_logic;
	enet_txd : OUT std_logic_vector(7 DOWNTO 0);
	enet_rx_clk : IN std_logic;
	enet_rx_er : IN std_logic;
	enet_rx_dv : IN std_logic;
	enet_rxd : IN std_logic_vector(7 DOWNTO 0);
	enet_crs : IN std_logic;
	enet_col : IN std_logic;
	enet_resetn : OUT std_logic;
	enet_mdc : OUT std_logic;
	enet_mdio : INOUT std_logic;
	enet_intn : IN std_logic;
	flash_a : OUT std_logic_vector(24 DOWNTO 0);
	flash_d : INOUT std_logic_vector(15 DOWNTO 0);
	flash_cen : OUT std_logic;
	flash_oen : OUT std_logic;
	flash_wen : OUT std_logic;
	flash_resetn : OUT std_logic;
	flash_byten : OUT std_logic;
	flash_rdybsyn : IN std_logic;
	user_dipsw : IN std_logic_vector(7 DOWNTO 0);
	user_led : OUT std_logic_vector(7 DOWNTO 0);
	user_pb : IN std_logic_vector(1 DOWNTO 0);
	user_reset : IN std_logic;
	pcie_smbclk : IN std_logic;
	pcie_smbdat : INOUT std_logic;
	pcie_perstn : IN std_logic;
	pcie_waken : OUT std_logic;
	pcie_led_x1 : OUT std_logic;
	pcie_led_x4 : OUT std_logic;
	pcie_led_x8 : OUT std_logic;
	hsma_tx_d_p : OUT std_logic_vector(16 DOWNTO 0);
	hsma_rx_d_p : IN std_logic_vector(16 DOWNTO 0);
	hsma_d : INOUT std_logic_vector(3 DOWNTO 0);
	hsma_clk_in0 : IN std_logic;
	hsma_clk_out0 : OUT std_logic;
	hsma_clk_in_p1 : IN std_logic;
	hsma_clk_out_p1 : OUT std_logic;
	hsma_clk_in_p2 : IN std_logic;
	hsma_clk_out_p2 : OUT std_logic;
	hsma_sda : INOUT std_logic;
	hsma_scl : OUT std_logic;
	hsma_led_tx : OUT std_logic;
	hsma_led_rx : OUT std_logic;
	hsmb_tx_d_p : OUT std_logic_vector(16 DOWNTO 0);
	hsmb_rx_d_p : IN std_logic_vector(16 DOWNTO 0);
	hsmb_d : INOUT std_logic_vector(3 DOWNTO 0);
	hsmb_clk_in0 : IN std_logic;
	hsmb_clk_out0 : OUT std_logic;
	hsmb_clk_in_p1 : IN std_logic;
	hsmb_clk_out_p1 : OUT std_logic;
	hsmb_clk_in_p2 : IN std_logic;
	hsmb_clk_out_p2 : OUT std_logic;
	hsmb_sda : INOUT std_logic;
	hsmb_scl : OUT std_logic;
	hsmb_led_tx : OUT std_logic;
	hsmb_led_rx : OUT std_logic;
	sfpa_txfault : IN std_logic;
	sfpa_txdisable : OUT std_logic;
	sfpa_mod0_prsntn : IN std_logic;
	sfpa_mod1_scl : OUT std_logic;
	sfpa_mod2_sda : INOUT std_logic;
	sfpa_ratesel : OUT std_logic;
	sfpa_los : IN std_logic;
	sfpa_led_tx : OUT std_logic;
	sfpa_led_rx : OUT std_logic;
	sfpb_txfault : IN std_logic;
	sfpb_txdisable : OUT std_logic;
	sfpb_mod0_prsntn : IN std_logic;
	sfpb_mod1_scl : OUT std_logic;
	sfpb_mod2_sda : INOUT std_logic;
	sfpb_ratesel : OUT std_logic;
	sfpb_los : IN std_logic;
	sfpb_led_tx : OUT std_logic;
	sfpb_led_rx : OUT std_logic
	);
END s2gx_pcie_top;

ARCHITECTURE structure OF s2gx_pcie_top IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk1_p : std_logic;
SIGNAL ww_clk2_p : std_logic;
SIGNAL ww_tsense_smb_clk : std_logic;
SIGNAL ww_alertn : std_logic;
SIGNAL ww_ddr2_a : std_logic_vector(14 DOWNTO 0);
SIGNAL ww_ddr2_ba : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_ddr2_dm : std_logic_vector(8 DOWNTO 0);
SIGNAL ww_ddr2_wen : std_logic;
SIGNAL ww_ddr2_rasn : std_logic;
SIGNAL ww_ddr2_casn : std_logic;
SIGNAL ww_ddr2_ck_p : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_ddr2_ck_n : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_ddr2_cke : std_logic;
SIGNAL ww_ddr2_csn : std_logic;
SIGNAL ww_ddr2_odt : std_logic;
SIGNAL ww_ddr2_sync_clk_out : std_logic;
SIGNAL ww_ddr2_sync_clk_in : std_logic;
SIGNAL ww_qdrii_a : std_logic_vector(18 DOWNTO 0);
SIGNAL ww_qdrii_d : std_logic_vector(35 DOWNTO 0);
SIGNAL ww_qdrii_q : std_logic_vector(35 DOWNTO 0);
SIGNAL ww_qdrii_rpsn : std_logic;
SIGNAL ww_qdrii_wpsn : std_logic;
SIGNAL ww_qdrii_bwsn : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_qdrii_k_p : std_logic;
SIGNAL ww_qdrii_k_n : std_logic;
SIGNAL ww_qdrii_cq_p : std_logic;
SIGNAL ww_qdrii_cq_n : std_logic;
SIGNAL ww_enet_gtx_clk : std_logic;
SIGNAL ww_enet_tx_clk : std_logic;
SIGNAL ww_enet_tx_er : std_logic;
SIGNAL ww_enet_tx_en : std_logic;
SIGNAL ww_enet_txd : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_enet_rx_clk : std_logic;
SIGNAL ww_enet_rx_er : std_logic;
SIGNAL ww_enet_rx_dv : std_logic;
SIGNAL ww_enet_rxd : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_enet_crs : std_logic;
SIGNAL ww_enet_col : std_logic;
SIGNAL ww_enet_resetn : std_logic;
SIGNAL ww_enet_mdc : std_logic;
SIGNAL ww_enet_intn : std_logic;
SIGNAL ww_flash_a : std_logic_vector(24 DOWNTO 0);
SIGNAL ww_flash_cen : std_logic;
SIGNAL ww_flash_oen : std_logic;
SIGNAL ww_flash_wen : std_logic;
SIGNAL ww_flash_resetn : std_logic;
SIGNAL ww_flash_byten : std_logic;
SIGNAL ww_flash_rdybsyn : std_logic;
SIGNAL ww_user_dipsw : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_user_led : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_user_pb : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_user_reset : std_logic;
SIGNAL ww_pcie_smbclk : std_logic;
SIGNAL ww_pcie_perstn : std_logic;
SIGNAL ww_pcie_waken : std_logic;
SIGNAL ww_pcie_led_x1 : std_logic;
SIGNAL ww_pcie_led_x4 : std_logic;
SIGNAL ww_pcie_led_x8 : std_logic;
SIGNAL ww_hsma_tx_d_p : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_hsma_rx_d_p : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_hsma_clk_in0 : std_logic;
SIGNAL ww_hsma_clk_out0 : std_logic;
SIGNAL ww_hsma_clk_in_p1 : std_logic;
SIGNAL ww_hsma_clk_out_p1 : std_logic;
SIGNAL ww_hsma_clk_in_p2 : std_logic;
SIGNAL ww_hsma_clk_out_p2 : std_logic;
SIGNAL ww_hsma_scl : std_logic;
SIGNAL ww_hsma_led_tx : std_logic;
SIGNAL ww_hsma_led_rx : std_logic;
SIGNAL ww_hsmb_tx_d_p : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_hsmb_rx_d_p : std_logic_vector(16 DOWNTO 0);
SIGNAL ww_hsmb_clk_in0 : std_logic;
SIGNAL ww_hsmb_clk_out0 : std_logic;
SIGNAL ww_hsmb_clk_in_p1 : std_logic;
SIGNAL ww_hsmb_clk_out_p1 : std_logic;
SIGNAL ww_hsmb_clk_in_p2 : std_logic;
SIGNAL ww_hsmb_clk_out_p2 : std_logic;
SIGNAL ww_hsmb_scl : std_logic;
SIGNAL ww_hsmb_led_tx : std_logic;
SIGNAL ww_hsmb_led_rx : std_logic;
SIGNAL ww_sfpa_txfault : std_logic;
SIGNAL ww_sfpa_txdisable : std_logic;
SIGNAL ww_sfpa_mod0_prsntn : std_logic;
SIGNAL ww_sfpa_mod1_scl : std_logic;
SIGNAL ww_sfpa_ratesel : std_logic;
SIGNAL ww_sfpa_los : std_logic;
SIGNAL ww_sfpa_led_tx : std_logic;
SIGNAL ww_sfpa_led_rx : std_logic;
SIGNAL ww_sfpb_txfault : std_logic;
SIGNAL ww_sfpb_txdisable : std_logic;
SIGNAL ww_sfpb_mod0_prsntn : std_logic;
SIGNAL ww_sfpb_mod1_scl : std_logic;
SIGNAL ww_sfpb_ratesel : std_logic;
SIGNAL ww_sfpb_los : std_logic;
SIGNAL ww_sfpb_led_tx : std_logic;
SIGNAL ww_sfpb_led_rx : std_logic;
SIGNAL \user_dipsw~combout\ : std_logic_vector(7 DOWNTO 0);

BEGIN

ww_clk1_p <= clk1_p;
ww_clk2_p <= clk2_p;
ww_tsense_smb_clk <= tsense_smb_clk;
ww_alertn <= alertn;
ddr2_a <= ww_ddr2_a;
ddr2_ba <= ww_ddr2_ba;
ddr2_dm <= ww_ddr2_dm;
ddr2_wen <= ww_ddr2_wen;
ddr2_rasn <= ww_ddr2_rasn;
ddr2_casn <= ww_ddr2_casn;
ddr2_ck_p <= ww_ddr2_ck_p;
ddr2_ck_n <= ww_ddr2_ck_n;
ddr2_cke <= ww_ddr2_cke;
ddr2_csn <= ww_ddr2_csn;
ddr2_odt <= ww_ddr2_odt;
ddr2_sync_clk_out <= ww_ddr2_sync_clk_out;
ww_ddr2_sync_clk_in <= ddr2_sync_clk_in;
qdrii_a <= ww_qdrii_a;
qdrii_d <= ww_qdrii_d;
ww_qdrii_q <= qdrii_q;
qdrii_rpsn <= ww_qdrii_rpsn;
qdrii_wpsn <= ww_qdrii_wpsn;
qdrii_bwsn <= ww_qdrii_bwsn;
qdrii_k_p <= ww_qdrii_k_p;
qdrii_k_n <= ww_qdrii_k_n;
ww_qdrii_cq_p <= qdrii_cq_p;
ww_qdrii_cq_n <= qdrii_cq_n;
enet_gtx_clk <= ww_enet_gtx_clk;
ww_enet_tx_clk <= enet_tx_clk;
enet_tx_er <= ww_enet_tx_er;
enet_tx_en <= ww_enet_tx_en;
enet_txd <= ww_enet_txd;
ww_enet_rx_clk <= enet_rx_clk;
ww_enet_rx_er <= enet_rx_er;
ww_enet_rx_dv <= enet_rx_dv;
ww_enet_rxd <= enet_rxd;
ww_enet_crs <= enet_crs;
ww_enet_col <= enet_col;
enet_resetn <= ww_enet_resetn;
enet_mdc <= ww_enet_mdc;
ww_enet_intn <= enet_intn;
flash_a <= ww_flash_a;
flash_cen <= ww_flash_cen;
flash_oen <= ww_flash_oen;
flash_wen <= ww_flash_wen;
flash_resetn <= ww_flash_resetn;
flash_byten <= ww_flash_byten;
ww_flash_rdybsyn <= flash_rdybsyn;
ww_user_dipsw <= user_dipsw;
user_led <= ww_user_led;
ww_user_pb <= user_pb;
ww_user_reset <= user_reset;
ww_pcie_smbclk <= pcie_smbclk;
ww_pcie_perstn <= pcie_perstn;
pcie_waken <= ww_pcie_waken;
pcie_led_x1 <= ww_pcie_led_x1;
pcie_led_x4 <= ww_pcie_led_x4;
pcie_led_x8 <= ww_pcie_led_x8;
hsma_tx_d_p <= ww_hsma_tx_d_p;
ww_hsma_rx_d_p <= hsma_rx_d_p;
ww_hsma_clk_in0 <= hsma_clk_in0;
hsma_clk_out0 <= ww_hsma_clk_out0;
ww_hsma_clk_in_p1 <= hsma_clk_in_p1;
hsma_clk_out_p1 <= ww_hsma_clk_out_p1;
ww_hsma_clk_in_p2 <= hsma_clk_in_p2;
hsma_clk_out_p2 <= ww_hsma_clk_out_p2;
hsma_scl <= ww_hsma_scl;
hsma_led_tx <= ww_hsma_led_tx;
hsma_led_rx <= ww_hsma_led_rx;
hsmb_tx_d_p <= ww_hsmb_tx_d_p;
ww_hsmb_rx_d_p <= hsmb_rx_d_p;
ww_hsmb_clk_in0 <= hsmb_clk_in0;
hsmb_clk_out0 <= ww_hsmb_clk_out0;
ww_hsmb_clk_in_p1 <= hsmb_clk_in_p1;
hsmb_clk_out_p1 <= ww_hsmb_clk_out_p1;
ww_hsmb_clk_in_p2 <= hsmb_clk_in_p2;
hsmb_clk_out_p2 <= ww_hsmb_clk_out_p2;
hsmb_scl <= ww_hsmb_scl;
hsmb_led_tx <= ww_hsmb_led_tx;
hsmb_led_rx <= ww_hsmb_led_rx;
ww_sfpa_txfault <= sfpa_txfault;
sfpa_txdisable <= ww_sfpa_txdisable;
ww_sfpa_mod0_prsntn <= sfpa_mod0_prsntn;
sfpa_mod1_scl <= ww_sfpa_mod1_scl;
sfpa_ratesel <= ww_sfpa_ratesel;
ww_sfpa_los <= sfpa_los;
sfpa_led_tx <= ww_sfpa_led_tx;
sfpa_led_rx <= ww_sfpa_led_rx;
ww_sfpb_txfault <= sfpb_txfault;
sfpb_txdisable <= ww_sfpb_txdisable;
ww_sfpb_mod0_prsntn <= sfpb_mod0_prsntn;
sfpb_mod1_scl <= ww_sfpb_mod1_scl;
sfpb_ratesel <= ww_sfpb_ratesel;
ww_sfpb_los <= sfpb_los;
sfpb_led_tx <= ww_sfpb_led_tx;
sfpb_led_rx <= ww_sfpb_led_rx;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\user_dipsw[0]~I\ : stratixiigx_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	ddioinclk_input => "negated_inclk",
	dqs_delay_buffer_mode => "none",
	dqs_out_mode => "none",
	inclk_input => "normal",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none",
	sim_dqs_delay_increment => 0,
	sim_dqs_intrinsic_delay => 0,
	sim_dqs_offset_increment => 0)
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_user_dipsw(0),
	combout => \user_dipsw~combout\(0));

\user_dipsw[1]~I\ : stratixiigx_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	ddioinclk_input => "negated_inclk",
	dqs_delay_buffer_mode => "none",
	dqs_out_mode => "none",
	inclk_input => "normal",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none",
	sim_dqs_delay_increment => 0,
	sim_dqs_intrinsic_delay => 0,
	sim_dqs_offset_increment => 0)
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_user_dipsw(1),
	combout => \user_dipsw~combout\(1));

\user_dipsw[2]~I\ : stratixiigx_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	ddioinclk_input => "negated_inclk",
	dqs_delay_buffer_mode => "none",
	dqs_out_mode => "none",
	inclk_input => "normal",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none",
	sim_dqs_delay_increment => 0,
	sim_dqs_intrinsic_delay => 0,
	sim_dqs_offset_increment => 0)
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_user_dipsw(2),
	combout => \user_dipsw~combout\(2));

\user_dipsw[3]~I\ : stratixiigx_io
-- pragma translate_off
GENERIC MAP (
	ddio_mode => "none",
	ddioinclk_input => "negated_inclk",
	dqs_delay_buffer_mode => "none",
	dqs_out_mode => "none",
	inclk_input => "normal",
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none",
	sim_dqs_delay_increment => 0,