s2gx_pcie_top.fit.rpt

基于SIIGX的PCIe的Kit

+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP2SGX90FF1508C3               ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
; Always Enable Input Buffers                        ; Off                            ; Off                            ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/golden_top/s2gx_pcie_top.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/golden_top/s2gx_pcie_top.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+------------------------------------------------+-----------------------+
; Resource                                       ; Usage                 ;
+------------------------------------------------+-----------------------+
; Total ALUTs                                    ; 0 / 72,768 ( 0 % )    ;
;     -- ALUTs Used                              ; 0                     ;
;         -- Combinational with no register      ; 0                     ;
;         -- Register only                       ; 0                     ;
;         -- Combinational with a register       ; 0                     ;
;     -- ALUTs Unavailable                       ; 0                     ;
;         -- Due to unpartnered 7 input function ; 0                     ;
;         -- Due to unpartnered 6 input function ; 0                     ;
;                                                ;                       ;
; ALUT usage by number of inputs                 ;                       ;
;     -- 7 input functions                       ; 0                     ;
;     -- 6 input functions                       ; 0                     ;
;     -- 5 input functions                       ; 0                     ;
;     -- 4 input functions                       ; 0                     ;
;     -- <=3 input functions                     ; 0                     ;
;     -- Register only                           ; 0                     ;
;                                                ;                       ;
; ALUTs without a partner                        ; 0                     ;
;     -- unpartnered 7 input functions           ; 0 / 0 ( 0 % )         ;
;     -- unpartnered 6 input functions           ; 0 / 0 ( 0 % )         ;