s2gx_pcie_top.fit.rpt

基于SIIGX的PCIe的Kit

Fitter report for s2gx_pcie_top
Mon Jul 24 12:03:04 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Equations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Non-Global High Fan-Out Signals
 17. Interconnect Usage Summary
 18. Fitter Device Options
 19. Advanced Data - General
 20. Advanced Data - Placement Preparation
 21. Advanced Data - Placement
 22. Advanced Data - Routing
 23. Fitter Messages
 24. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------+
; Fitter Summary                                                            ;
+--------------------------------+------------------------------------------+
; Fitter Status                  ; Successful - Mon Jul 24 12:03:03 2006    ;
; Quartus II Version             ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name                  ; s2gx_pcie_top                            ;
; Top-level Entity Name          ; s2gx_pcie_top                            ;
; Family                         ; Stratix II GX                            ;
; Device                         ; EP2SGX90FF1508C3                         ;
; Timing Models                  ; Preliminary                              ;
; Total ALUTs                    ; 0 / 72,768 ( 0 % )                       ;
; Total registers                ; 0                                        ;
; Total pins                     ; 522 / 739 ( 71 % )                       ;
; Total virtual pins             ; 0                                        ;
; Total memory bits              ; 0 / 4,520,448 ( 0 % )                    ;
; DSP block 9-bit elements       ; 0 / 384 ( 0 % )                          ;
; Total GXB Receiver Channels    ; 0 / 16 ( 0 % )                           ;
; Total GXB Transmitter Channels ; 0 / 16 ( 0 % )                           ;
; Total PLLs                     ; 0 / 8 ( 0 % )                            ;
; Total DLLs                     ; 0 / 2 ( 0 % )                            ;
+--------------------------------+------------------------------------------+