📄 ddr2_topecc_extraction_data.txt
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array_name= min_paths_for_each_half_dq_0
dq_2_ddio 1143
ddio_2_core 566
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_1
dq_2_ddio 1153
ddio_2_core 579
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_2
dq_2_ddio 1143
ddio_2_core 558
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_3
dq_2_ddio 1153
ddio_2_core 570
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_4
dq_2_ddio 1143
ddio_2_core 462
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_5
dq_2_ddio 1153
ddio_2_core 472
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_6
dq_2_ddio 1143
ddio_2_core 368
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_7
dq_2_ddio 1153
ddio_2_core 471
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_8
dq_2_ddio 1143
ddio_2_core 377
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_9
dq_2_ddio 1153
ddio_2_core 395
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_10
dq_2_ddio 1143
ddio_2_core 368
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_11
dq_2_ddio 1153
ddio_2_core 472
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_12
dq_2_ddio 1143
ddio_2_core 471
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_13
dq_2_ddio 1153
ddio_2_core 477
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_14
dq_2_ddio 1143
ddio_2_core 562
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_15
dq_2_ddio 1153
ddio_2_core 583
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 783
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_16
dq_2_ddio 1143
ddio_2_core 535
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_17
dq_2_ddio 1153
ddio_2_core 482
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_18
dq_2_ddio 1143
ddio_2_core 462
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_19
dq_2_ddio 1153
ddio_2_core 488
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_20
dq_2_ddio 1143
ddio_2_core 459
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_21
dq_2_ddio 1153
ddio_2_core 484
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_22
dq_2_ddio 1143
ddio_2_core 463
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_23
dq_2_ddio 1153
ddio_2_core 0
core_2_reg 708
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_24
dq_2_ddio 1143
ddio_2_core 371
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_25
dq_2_ddio 1153
ddio_2_core 398
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_26
dq_2_ddio 1143
ddio_2_core 455
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_27
dq_2_ddio 1153
ddio_2_core 478
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_28
dq_2_ddio 1143
ddio_2_core 473
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_29
dq_2_ddio 1153
ddio_2_core 481
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_30
dq_2_ddio 1143
ddio_2_core 468
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_31
dq_2_ddio 1153
ddio_2_core 564
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 731
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_32
dq_2_ddio 1143
ddio_2_core 455
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_33
dq_2_ddio 1153
ddio_2_core 470
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_34
dq_2_ddio 1143
ddio_2_core 452
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_35
dq_2_ddio 1153
ddio_2_core 546
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_36
dq_2_ddio 1143
ddio_2_core 448
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_37
dq_2_ddio 1153
ddio_2_core 465
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 715
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_38
dq_2_ddio 1143
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