ddr2_v340_ecc.tan.qmsg

基于SIIGX的PCIe的Kit

{ "Info" "ITDB_FULL_SLACK_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1 register ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\] register ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg 381 ps " "Info: Slack time is 381 ps for clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1\" between source register \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\]\" and destination register \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.766 ns + Largest register register " "Info: + Largest register to register requirement is 1.766 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.250 ns + " "Info: + Setup relationship between source and destination is 2.250 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.142 ns " "Info: + Latch edge is 5.142 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1 3.000 ns -3.858 ns  50 " "Info: Clock period of Destination clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1\" is 3.000 ns with  offset of -3.858 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 2.892 ns " "Info: - Launch edge is 2.892 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 3.000 ns -3.108 ns  50 " "Info: Clock period of Source clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" is 3.000 ns with  offset of -3.108 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.268 ns + Largest " "Info: + Largest clock skew is -0.268 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1 destination 2.936 ns + Shortest register " "Info: + Shortest clock path from clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1\" to destination register is 2.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1 1 CLK PLL_6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 1; CLK Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.000 ns) 1.303 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G7 324 " "Info: 2: + IC(1.303 ns) + CELL(0.000 ns) = 1.303 ns; Loc. = CLKCTRL_G7; Fanout = 324; COMB Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 868 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(0.290 ns) 2.936 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg 3 REG IOC_X13_Y0_N3 1 " "Info: 3: + IC(1.343 ns) + CELL(0.290 ns) = 2.936 ns; Loc. = IOC_X13_Y0_N3; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.290 ns ( 9.88 % ) " "Info: Total cell delay = 0.290 ns ( 9.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.646 ns ( 90.12 % ) " "Info: Total interconnect delay = 2.646 ns ( 90.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } { 0.000ns 1.303ns 1.343ns } { 0.000ns 0.000ns 0.290ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 source 3.204 ns - Longest register " "Info: - Longest clock path from clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" to source register is 3.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 8; CLK Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.000 ns) 1.303 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G5 1936 " "Info: 2: + IC(1.303 ns) + CELL(0.000 ns) = 1.303 ns; Loc. = CLKCTRL_G5; Fanout = 1936; COMB Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.283 ns) + CELL(0.618 ns) 3.204 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\] 3 REG LCFF_X25_Y2_N1 1 " "Info: 3: + IC(1.283 ns) + CELL(0.618 ns) = 3.204 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.901 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } "NODE_NAME" } } { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 787 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.618 ns ( 19.29 % ) " "Info: Total cell delay = 0.618 ns ( 19.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.586 ns ( 80.71 % ) " "Info: Total interconnect delay = 2.586 ns ( 80.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } { 0.000ns 1.303ns 1.283ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } { 0.000ns 1.303ns 1.343ns } { 0.000ns 0.000ns 0.290ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } { 0.000ns 1.303ns 1.283ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 787 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.122 ns - " "Info: - Micro setup delay of destination is 0.122 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.936 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } { 0.000ns 1.303ns 1.343ns } { 0.000ns 0.000ns 0.290ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.204 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } { 0.000ns 1.303ns 1.283ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.385 ns - Longest register register " "Info: - Longest register to register delay is 1.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\] 1 REG LCFF_X25_Y2_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|wdata_r\[7\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] } "NODE_NAME" } } { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 787 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.107 ns) + CELL(0.278 ns) 1.385 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg 2 REG IOC_X13_Y0_N3 1 " "Info: 2: + IC(1.107 ns) + CELL(0.278 ns) = 1.385 ns; Loc. = IOC_X13_Y0_N3; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|\\g_dq_io:7:dq_io~data_in_reg'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7] ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.278 ns ( 20.07 % ) " "Info: Total cell delay = 0.278 ns ( 20.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.107 ns ( 79.93 % ) " "Info: Total interconnect delay = 1.107 ns ( 79.93 % )" {  } {  } 0 0 "Total intercon