ddr2_v340_ecc.tan.qmsg

基于SIIGX的PCIe的Kit

{ "Info" "ITDB_FULL_SLACK_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 register ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid register ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\] -420 ps " "Info: Slack time is -420 ps for clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" between source register \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid\" and destination register \"ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "292.4 MHz 3.42 ns " "Info: Fmax is 292.4 MHz (period= 3.42 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.821 ns + Largest register register " "Info: + Largest register to register requirement is 2.821 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "3.000 ns + " "Info: + Setup relationship between source and destination is 3.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -0.108 ns " "Info: + Latch edge is -0.108 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 3.000 ns -3.108 ns  50 " "Info: Clock period of Destination clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" is 3.000 ns with  offset of -3.108 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -3.108 ns " "Info: - Launch edge is -3.108 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 3.000 ns -3.108 ns  50 " "Info: Clock period of Source clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" is 3.000 ns with  offset of -3.108 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.005 ns + Largest " "Info: + Largest clock skew is 0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 destination 3.179 ns + Shortest register " "Info: + Shortest clock path from clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" to destination register is 3.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 8; CLK Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.000 ns) 1.303 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G5 1936 " "Info: 2: + IC(1.303 ns) + CELL(0.000 ns) = 1.303 ns; Loc. = CLKCTRL_G5; Fanout = 1936; COMB Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.618 ns) 3.179 ns ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\] 3 REG LCFF_X55_Y3_N7 3 " "Info: 3: + IC(1.258 ns) + CELL(0.618 ns) = 3.179 ns; Loc. = LCFF_X55_Y3_N7; Fanout = 3; REG Node = 'ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.876 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.618 ns ( 19.44 % ) " "Info: Total cell delay = 0.618 ns ( 19.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.561 ns ( 80.56 % ) " "Info: Total interconnect delay = 2.561 ns ( 80.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.303ns 1.258ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 source 3.174 ns - Longest register " "Info: - Longest clock path from clock \"ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0\" to source register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0 1 CLK PLL_6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_6; Fanout = 8; CLK Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.303 ns) + CELL(0.000 ns) 1.303 ns ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G5 1936 " "Info: 2: + IC(1.303 ns) + CELL(0.000 ns) = 1.303 ns; Loc. = CLKCTRL_G5; Fanout = 1936; COMB Node = 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.618 ns) 3.174 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid 3 REG LCFF_X56_Y5_N7 84 " "Info: 3: + IC(1.253 ns) + CELL(0.618 ns) = 3.174 ns; Loc. = LCFF_X56_Y5_N7; Fanout = 84; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.871 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.618 ns ( 19.47 % ) " "Info: Total cell delay = 0.618 ns ( 19.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.556 ns ( 80.53 % ) " "Info: Total interconnect delay = 2.556 ns ( 80.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } { 0.000ns 1.303ns 1.253ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.303ns 1.258ns } { 0.000ns 0.000ns 0.618ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } { 0.000ns 1.303ns 1.253ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" 95 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns - " "Info: - Micro setup delay of destination is 0.090 ns" {  } { { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.303ns 1.258ns } { 0.000ns 0.000ns 0.618ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } { 0.000ns 1.303ns 1.253ns } { 0.000ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.241 ns - Longest register register " "Info: - Longest register to register delay is 3.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid 1 REG LCFF_X56_Y5_N7 84 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y5_N7; Fanout = 84; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|auk_ddr_controller:ddr_control\|local_rdata_valid'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.053 ns) 1.325 ns ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\]~5741 2 COMB LCCOMB_X43_Y3_N16 71 " "Info: 2: + IC(1.272 ns) + CELL(0.053 ns) = 1.325 ns; Loc. = LCCOMB_X43_Y3_N16; Fanout = 71; COMB Node = 'ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\]~5741'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 } "NODE_NAME" } } { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.746 ns) 3.241 ns ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\] 3 REG LCFF_X55_Y3_N7 3 " "Info: 3: + IC(1.170 ns) + CELL(0.746 ns) = 3.241 ns; Loc. = LCFF_X55_Y3_N7; Fanout = 3; REG Node = 'ddr2_topecc_example_driver:driver\|example_lfsr8:LFSRGEN_0_lfsr_inst\|lfsr_data\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.916 ns" { ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" "" { Text "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.799 ns ( 24.65 % ) " "Info: Total cell delay = 0.799 ns ( 24.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.442 ns ( 75.35 % ) " "Info: Total interconnect delay = 2.442 ns ( 75.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.241 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.241 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.272ns 1.170ns } { 0.000ns 0.053ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.179 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.303ns 1.258ns } { 0.000ns 0.000ns 0.618ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0~clkctrl ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid } { 0.000ns 1.303ns 1.253ns } { 0.000ns 0.000ns 0.618ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.241 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.241 ns" { ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]~5741 ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0] } { 0.000ns 1.272ns 1.170ns } { 0.000ns 0.053ns 0.746ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0' 77 " "Warning: Can't achieve timing requirement Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst\|altpll:altpll_component\|_clk0' along 77 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}