ddr2_v340_ecc.tan.qmsg

基于SIIGX的PCIe的Kit

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "18 " "Warning: Found 18 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:2:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:5:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:4:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:6:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_clk\[0\] " "Info: Detected gated clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_clk\[0\]\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 114 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_clk\[0\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_io~regout " "Info: Detected ripple clock \"ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_io~regout\" as buffer" {  } { { "ddr2_topecc_auk_ddr_dqs_group.v" "" { Text "F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v" 949 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ddr2_topecc:ddr2_topecc_ddr_sdram\|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst\|ddr2_topecc_auk_ddr_datapath:ddr_io\|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:3:g_ddr_io\|dqs_io~regout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}