ddr2_v340_ecc.hif

基于SIIGX的PCIe的Kit

b7e8db7618dee9a34dc610899f8dd422
d:|altera|70|quartus|libraries|megafunctions|apexii_ddio.inc
9ecf3629f117ddbdda4ee130df2745fb
d:|altera|70|quartus|libraries|megafunctions|stratix_ddio.inc
af3f2ea6e1d6d7735ae08ecf6981c85f
d:|altera|70|quartus|libraries|megafunctions|cyclone_ddio.inc
c329e6be394e97acfa5ea438e9abd6
d:|altera|70|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|70|quartus|libraries|megafunctions|stratix_lcell.inc
1aad1342a15da19fe8b79bc4e5ad56
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:2:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|altddio_out:dm_pin
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io|altddio_out:dm_pin
}
# end
# entity
ddio_out_tkf
# storage
db|ddr2_v340_ecc.(22).cnf
db|ddr2_v340_ecc.(22).cnf
# case_insensitive
# source_file
db|ddio_out_tkf.tdf
ae54376a4f9d3b7d54d81bcedfb6cf6
6
# used_port {
outclock
-1
3
dataout0
-1
3
datain_l0
-1
3
datain_h0
-1
3
aclr
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:2:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io|altddio_out:dm_pin|ddio_out_tkf:auto_generated
}
# end
# entity
ddr2_topecc_example_driver
# storage
db|ddr2_v340_ecc.(23).cnf
db|ddr2_v340_ecc.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr2_topecc_example_driver.v
bf91eb5b0eb716e2f678fb8f6745796
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
ddr2_topecc_example_driver:driver
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(24).cnf
db|ddr2_v340_ecc.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
1
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(25).cnf
db|ddr2_v340_ecc.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
11
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_1_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(26).cnf
db|ddr2_v340_ecc.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
21
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_2_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(27).cnf
db|ddr2_v340_ecc.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
31
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_3_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(28).cnf
db|ddr2_v340_ecc.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
41
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_4_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(29).cnf
db|ddr2_v340_ecc.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
51
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_5_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(30).cnf
db|ddr2_v340_ecc.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
61
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_6_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(31).cnf
db|ddr2_v340_ecc.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
71
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_7_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(32).cnf
db|ddr2_v340_ecc.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
81
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_8_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(33).cnf
db|ddr2_v340_ecc.(33).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
91
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_9_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(34).cnf
db|ddr2_v340_ecc.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
101
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_10_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(35).cnf
db|ddr2_v340_ecc.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
111
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_11_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(36).cnf
db|ddr2_v340_ecc.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
121
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_12_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(37).cnf
db|ddr2_v340_ecc.(37).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
131
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_13_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(38).cnf
db|ddr2_v340_ecc.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
141
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_14_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(39).cnf
db|ddr2_v340_ecc.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
151
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_15_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(40).cnf
db|ddr2_v340_ecc.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
161
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_16_lfsr_inst
}
# end
# entity
example_lfsr8
# storage
db|ddr2_v340_ecc.(41).cnf
db|ddr2_v340_ecc.(41).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
E:|data|SIIGX_PCIe_Kit|Examples|ManufacturingTestDesigns|ddr2_v340_ecc_restored|altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|example_lfsr8.v
6085d157d51f3dc1883d889bb997f9f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seed
171
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_17_lfsr_inst
}
# end
# entity
ddr_pll_stratixii
# storage
db|ddr2_v340_ecc.(42).cnf
db|ddr2_v340_ecc.(42).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr_pll_stratixii.v
ee1bd0b1e04f9e46efc17930c526fe9a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
ddr_pll_stratixii:g_stratixpll_ddr_pll_inst
}
# end
# entity
altpll
# storage
db|ddr2_v340_ecc.(43).cnf
db|ddr2_v340_ecc.(43).cnf
# case_insensitive
# source_file
d:|altera|70|quartus|libraries|megafunctions|altpll.tdf
9948948e9c204c786e29bcceb2be7f
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
10000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_SIGNED_DEC
USR
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
333333
PARAMETER_SIGNED_DEC
USR
CLK2_MULTIPLY_BY
333333
PARAMETER_SIGNED_DEC
USR
CLK1_MULTIPLY_BY
333333
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
333333
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
100000
PARAMETER_SIGNED_DEC
USR
CLK2_DIVIDE_BY
100000
PARAMETER_SIGNED_DEC
USR
CLK1_DIVIDE_BY
100000
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
100000
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK2_PHASE_SHIFT
2267
PARAMETER_UNKNOWN
USR
CLK1_PHASE_SHIFT
-750
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK2_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF