ddr2_v340_ecc.hif

基于SIIGX的PCIe的Kit

3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a161
-1
3
data_a160
-1
3
data_a16
-1
3
data_a159
-1
3
data_a158
-1
3
data_a157
-1
3
data_a156
-1
3
data_a155
-1
3
data_a154
-1
3
data_a153
-1
3
data_a152
-1
3
data_a151
-1
3
data_a150
-1
3
data_a15
-1
3
data_a149
-1
3
data_a148
-1
3
data_a147
-1
3
data_a146
-1
3
data_a145
-1
3
data_a144
-1
3
data_a143
-1
3
data_a142
-1
3
data_a141
-1
3
data_a140
-1
3
data_a14
-1
3
data_a139
-1
3
data_a138
-1
3
data_a137
-1
3
data_a136
-1
3
data_a135
-1
3
data_a134
-1
3
data_a133
-1
3
data_a132
-1
3
data_a131
-1
3
data_a130
-1
3
data_a13
-1
3
data_a129
-1
3
data_a128
-1
3
data_a127
-1
3
data_a126
-1
3
data_a125
-1
3
data_a124
-1
3
data_a123
-1
3
data_a122
-1
3
data_a121
-1
3
data_a120
-1
3
data_a12
-1
3
data_a119
-1
3
data_a118
-1
3
data_a117
-1
3
data_a116
-1
3
data_a115
-1
3
data_a114
-1
3
data_a113
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo|scfifo_e691:auto_generated|a_dpfifo_7u11:dpfifo|altsyncram_a6e1:FIFOram
}
# end
# entity
cntr_bu8
# storage
db|ddr2_v340_ecc.(8).cnf
db|ddr2_v340_ecc.(8).cnf
# case_insensitive
# source_file
db|cntr_bu8.tdf
f5615f300ae813d50e7082bf8653d0
6
# used_port {
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo|scfifo_e691:auto_generated|a_dpfifo_7u11:dpfifo|cntr_bu8:rd_ptr_msb
}
# end
# entity
cntr_qs7
# storage
db|ddr2_v340_ecc.(9).cnf
db|ddr2_v340_ecc.(9).cnf
# case_insensitive
# source_file
db|cntr_qs7.tdf
d56a2ebf6fca4e6ace13e1d25410c449
6
# used_port {
updown
-1
3
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo|scfifo_e691:auto_generated|a_dpfifo_7u11:dpfifo|cntr_qs7:usedw_counter
}
# end
# entity
cntr_cu8
# storage
db|ddr2_v340_ecc.(10).cnf
db|ddr2_v340_ecc.(10).cnf
# case_insensitive
# source_file
db|cntr_cu8.tdf
326b8eec26bd457749eeb23f4f549f6
6
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo|scfifo_e691:auto_generated|a_dpfifo_7u11:dpfifo|cntr_cu8:wr_ptr
}
# end
# entity
auk_ddr_input_buf
# storage
db|ddr2_v340_ecc.(11).cnf
db|ddr2_v340_ecc.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_input_buf.vhd
2d9476827c687c67ea727c7be3648e5
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
glocal_data_bits
144
PARAMETER_SIGNED_DEC
USR
glocal_burst_len
2
PARAMETER_SIGNED_DEC
USR
glocal_burst_len_bits
2
PARAMETER_SIGNED_DEC
USR
gfamily
Stratix
PARAMETER_STRING
USR
gmem_chip_bits
0
PARAMETER_SIGNED_DEC
USR
gmem_row_bits
13
PARAMETER_SIGNED_DEC
USR
gmem_bank_bits
2
PARAMETER_SIGNED_DEC
USR
gmem_col_bits
10
PARAMETER_SIGNED_DEC
USR
gbuffer_bits
30
PARAMETER_SIGNED_DEC
USR
 constraint(cs_addr)
0 downto 0
PARAMETER_STRING
USR
 constraint(row_addr)
12 downto 0
PARAMETER_STRING
USR
 constraint(bank_addr)
1 downto 0
PARAMETER_STRING
USR
 constraint(col_addr)
8 downto 0
PARAMETER_STRING
USR
 constraint(size)
1 downto 0
PARAMETER_STRING
USR
 constraint(buf_output)
29 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_functions.vhd
49eb59a6bf7e517337141218160f414
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_input_buf:in_buf
}
# end
# entity
custom_fifo
# storage
db|ddr2_v340_ecc.(12).cnf
db|ddr2_v340_ecc.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_input_buf.vhd
2d9476827c687c67ea727c7be3648e5
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
gwidth
30
PARAMETER_SIGNED_DEC
USR
gdepth
4
PARAMETER_SIGNED_DEC
USR
 constraint(data)
29 downto 0
PARAMETER_STRING
USR
 constraint(q)
29 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_functions.vhd
49eb59a6bf7e517337141218160f414
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_input_buf:in_buf|custom_fifo:my_fifo
}
# end
# entity
auk_ddr_bank_details
# storage
db|ddr2_v340_ecc.(13).cnf
db|ddr2_v340_ecc.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_bank_details.vhd
54f14f6a6b314a49f5fdfd8e8c49190
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
gmem_chip_bits
0
PARAMETER_SIGNED_DEC
USR
gmem_row_bits
13
PARAMETER_SIGNED_DEC
USR
gmem_bank_bits
2
PARAMETER_SIGNED_DEC
USR
 constraint(open_this_row)
12 downto 0
PARAMETER_STRING
USR
 constraint(in_this_bank)
1 downto 0
PARAMETER_STRING
USR
 constraint(cs_ba_addr)
1 downto 0
PARAMETER_STRING
USR
 constraint(openrow)
12 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_functions.vhd
49eb59a6bf7e517337141218160f414
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_bank_details:bank_man
}
# end
# entity
auk_ddr2_init
# storage
db|ddr2_v340_ecc.(14).cnf
db|ddr2_v340_ecc.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr2_init.vhd
58755e3f2273e223391b39f186bcefc4
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
gmem_row_bits
13
PARAMETER_SIGNED_DEC
USR
gmem_bank_bits
2
PARAMETER_SIGNED_DEC
USR
 constraint(init_addr)
12 downto 0
PARAMETER_STRING
USR
 constraint(init_ba)
1 downto 0
PARAMETER_STRING
USR
 constraint(mem_tcl)
2 downto 0
PARAMETER_STRING
USR
 constraint(mem_bl)
2 downto 0
PARAMETER_STRING
USR
 constraint(mem_odt)
1 downto 0
PARAMETER_STRING
USR
 constraint(mem_twr)
2 downto 0
PARAMETER_STRING
USR
 constraint(mem_tinit_time)
15 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_functions.vhd
49eb59a6bf7e517337141218160f414
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr2_init:\g_ddr2_init:init_block
}
# end
# entity
auk_ddr_timers
# storage
db|ddr2_v340_ecc.(15).cnf
db|ddr2_v340_ecc.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_timers.vhd
3e1ce1b763c3e8bd22cfa115fc6de66
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
gmem_chip_bits
0
PARAMETER_SIGNED_DEC
USR
gmem_bank_bits
2
PARAMETER_SIGNED_DEC
USR
 constraint(mem_tras)
3 downto 0
PARAMETER_STRING
USR
 constraint(mem_twr)
2 downto 0
PARAMETER_STRING
USR
}
# include_file {
altera|MegaCore|ddr_ddr2_sdram-v3.4.0|lib|auk_ddr_functions.vhd
49eb59a6bf7e517337141218160f414
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:0:bank_timer
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:1:bank_timer
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:2:bank_timer
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:3:bank_timer
}
# end
# entity
ddr2_topecc_auk_ddr_datapath
# storage
db|ddr2_v340_ecc.(16).cnf
db|ddr2_v340_ecc.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr2_topecc_auk_ddr_datapath.v
b670622134b2f57259136f4c2c218b44
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
gstratixii_dll_delay_buffer_mode
high
PARAMETER_STRING
USR
gstratixii_dqs_phase
9000
PARAMETER_SIGNED_DEC
USR
gstratixii_dqs_out_mode
delay_chain3
PARAMETER_STRING
USR
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io
}
# end
# entity
ddr2_topecc_auk_ddr_clk_gen
# storage
db|ddr2_v340_ecc.(17).cnf
db|ddr2_v340_ecc.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr2_topecc_auk_ddr_clk_gen.v
29fddb6a4c774834dc54d297d97d318
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen
}
# end
# entity
altddio_out
# storage
db|ddr2_v340_ecc.(18).cnf
db|ddr2_v340_ecc.(18).cnf
# case_insensitive
# source_file
d:|altera|70|quartus|libraries|megafunctions|altddio_out.tdf
f538382b881ee244d348f1073a692e4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
3
PARAMETER_SIGNED_DEC
USR
POWER_UP_HIGH
OFF
PARAMETER_UNKNOWN
USR
OE_REG
UNUSED
PARAMETER_UNKNOWN
DEF
extend_oe_disable
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix II
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix II GX
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
ddio_out_t6f
PARAMETER_UNKNOWN
USR
}
# used_port {
outclock
-1
3
dataout
-1
3
datain_h
-1
1
datain_l
-1
2
}
# include_file {
d:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
d:|altera|70|quartus|libraries|megafunctions|mercury_ddio.inc
b7e8db7618dee9a34dc610899f8dd422
d:|altera|70|quartus|libraries|megafunctions|apexii_ddio.inc
9ecf3629f117ddbdda4ee130df2745fb
d:|altera|70|quartus|libraries|megafunctions|stratix_ddio.inc
af3f2ea6e1d6d7735ae08ecf6981c85f
d:|altera|70|quartus|libraries|megafunctions|cyclone_ddio.inc
c329e6be394e97acfa5ea438e9abd6
d:|altera|70|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|70|quartus|libraries|megafunctions|stratix_lcell.inc
1aad1342a15da19fe8b79bc4e5ad56
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n
}
# end
# entity
ddio_out_t6f
# storage
db|ddr2_v340_ecc.(19).cnf
db|ddr2_v340_ecc.(19).cnf
# case_insensitive
# source_file
db|ddio_out_t6f.tdf
82ea8c566d6da76cdcd6ae764eb5af5a
6
# used_port {
outclock
-1
3
dataout2
-1
3
dataout1
-1
3
dataout0
-1
3
datain_l2
-1
3
datain_l1
-1
3
datain_l0
-1
3
datain_h2
-1
3
datain_h1
-1
3
datain_h0
-1
3
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p|ddio_out_t6f:auto_generated
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n|ddio_out_t6f:auto_generated
}
# end
# entity
ddr2_topecc_auk_ddr_dqs_group
# storage
db|ddr2_v340_ecc.(20).cnf
db|ddr2_v340_ecc.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr2_topecc_auk_ddr_dqs_group.v
9e23fd4a0805ac52148254fb460beab
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
gSTRATIXII_DQS_OUT_MODE
delay_chain3
PARAMETER_STRING
USR
gSTRATIXII_DLL_DELAY_BUFFER_MODE
high
PARAMETER_STRING
USR
gDLL_INPUT_FREQUENCY
3000ps
PARAMETER_STRING
USR
gSTRATIXII_DQS_PHASE
9000
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:2:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io
ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io
}
# end
# entity
altddio_out
# storage
db|ddr2_v340_ecc.(21).cnf
db|ddr2_v340_ecc.(21).cnf
# case_insensitive
# source_file
d:|altera|70|quartus|libraries|megafunctions|altddio_out.tdf
f538382b881ee244d348f1073a692e4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
1
PARAMETER_SIGNED_DEC
USR
POWER_UP_HIGH
OFF
PARAMETER_UNKNOWN
USR
OE_REG
UNUSED
PARAMETER_UNKNOWN
DEF
extend_oe_disable
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix II
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix II GX
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
ddio_out_tkf
PARAMETER_UNKNOWN
USR
}
# used_port {
outclock
-1
3
dataout
-1
3
datain_l
-1
3
datain_h
-1
3
aclr
-1
3
outclocken
-1
2
oe
-1
2
}
# include_file {
d:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
d:|altera|70|quartus|libraries|megafunctions|mercury_ddio.inc