ddr2_v340_ecc.smp_dump.txt

基于SIIGX的PCIe的Kit

State Machine - |ddr2_v340_ecc|ddr2_topecc_example_driver:driver|state
Name state.1000 state.0101 state.0001 state.1010 state.0010 state.1100 state.1101 state.0100 state.1011 state.0011 state.0110 state.0111 state.0000 
state.0000 0 0 0 0 0 0 0 0 0 0 0 0 0 
state.0111 0 0 0 0 0 0 0 0 0 0 0 1 1 
state.0110 0 0 0 0 0 0 0 0 0 0 1 0 1 
state.0011 0 0 0 0 0 0 0 0 0 1 0 0 1 
state.1011 0 0 0 0 0 0 0 0 1 0 0 0 1 
state.0100 0 0 0 0 0 0 0 1 0 0 0 0 1 
state.1101 0 0 0 0 0 0 1 0 0 0 0 0 1 
state.1100 0 0 0 0 0 1 0 0 0 0 0 0 1 
state.0010 0 0 0 0 1 0 0 0 0 0 0 0 1 
state.1010 0 0 0 1 0 0 0 0 0 0 0 0 1 
state.0001 0 0 1 0 0 0 0 0 0 0 0 0 1 
state.0101 0 1 0 0 0 0 0 0 0 0 0 0 1 
state.1000 1 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |ddr2_v340_ecc|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|state
Name state.s_writing state.s_reading state.s_holding state.s_wait_for_write_data state.s_write state.s_wait_before_read state.s_read state.s_activate state.s_idle state.s_refresh state.s_precharge state.s_wait_for_init_done 
state.s_wait_for_init_done 0 0 0 0 0 0 0 0 0 0 0 0 
state.s_precharge 0 0 0 0 0 0 0 0 0 0 1 1 
state.s_refresh 0 0 0 0 0 0 0 0 0 1 0 1 
state.s_idle 0 0 0 0 0 0 0 0 1 0 0 1 
state.s_activate 0 0 0 0 0 0 0 1 0 0 0 1 
state.s_read 0 0 0 0 0 0 1 0 0 0 0 1 
state.s_wait_before_read 0 0 0 0 0 1 0 0 0 0 0 1 
state.s_write 0 0 0 0 1 0 0 0 0 0 0 1 
state.s_wait_for_write_data 0 0 0 1 0 0 0 0 0 0 0 1 
state.s_holding 0 0 1 0 0 0 0 0 0 0 0 1 
state.s_reading 0 1 0 0 0 0 0 0 0 0 0 1 
state.s_writing 1 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |ddr2_v340_ecc|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr2_init:\g_ddr2_init:init_block|ddr2_init_state
Name ddr2_init_state.s_init2_done ddr2_init_state.s_init2_elmr_ocd_2 ddr2_init_state.s_init2_elmr_ocd ddr2_init_state.s_init2_lmr_2 ddr2_init_state.s_init2_rfsh_2 ddr2_init_state.s_init2_rfsh ddr2_init_state.s_init2_pch_2 ddr2_init_state.s_init2_lmr ddr2_init_state.s_init2_elmr ddr2_init_state.s_init2_elmr3 ddr2_init_state.s_init2_elmr2 ddr2_init_state.s_init2_pch ddr2_init_state.s_init2_wait 
ddr2_init_state.s_init2_wait 0 0 0 0 0 0 0 0 0 0 0 0 0 
ddr2_init_state.s_init2_pch 0 0 0 0 0 0 0 0 0 0 0 1 1 
ddr2_init_state.s_init2_elmr2 0 0 0 0 0 0 0 0 0 0 1 0 1 
ddr2_init_state.s_init2_elmr3 0 0 0 0 0 0 0 0 0 1 0 0 1 
ddr2_init_state.s_init2_elmr 0 0 0 0 0 0 0 0 1 0 0 0 1 
ddr2_init_state.s_init2_lmr 0 0 0 0 0 0 0 1 0 0 0 0 1 
ddr2_init_state.s_init2_pch_2 0 0 0 0 0 0 1 0 0 0 0 0 1 
ddr2_init_state.s_init2_rfsh 0 0 0 0 0 1 0 0 0 0 0 0 1 
ddr2_init_state.s_init2_rfsh_2 0 0 0 0 1 0 0 0 0 0 0 0 1 
ddr2_init_state.s_init2_lmr_2 0 0 0 1 0 0 0 0 0 0 0 0 1 
ddr2_init_state.s_init2_elmr_ocd 0 0 1 0 0 0 0 0 0 0 0 0 1 
ddr2_init_state.s_init2_elmr_ocd_2 0 1 0 0 0 0 0 0 0 0 0 0 1 
ddr2_init_state.s_init2_done 1 0 0 0 0 0 0 0 0 0 0 0 1