ddio_out_t6f.tdf

基于SIIGX的PCIe的Kit

--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II GX" INVERT_OUTPUT="OFF" POWER_UP_HIGH="OFF" WIDTH=3 datain_h datain_l dataout outclock
--VERSION_BEGIN 6.0 cbx_altddio_out 2006:03:03:09:14:02:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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FUNCTION stratixiigx_io (areset, datain, ddiodatain, ddioinclk, delayctrlin[5..0], dqsupdateen, inclk, inclkena, linkin, oe, offsetctrlin[5..0], outclk, outclkena, sreset, terminationcontrol[13..0])
WITH ( 	BUS_HOLD,	DDIO_MODE,	DDIOINCLK_INPUT,	DQS_CTRL_LATCHES_ENABLE,	DQS_DELAY_BUFFER_MODE,	DQS_EDGE_DETECT_ENABLE,	DQS_INPUT_FREQUENCY,	DQS_OFFSETCTRL_ENABLE,	DQS_OUT_MODE,	DQS_PHASE_SHIFT,	EXTEND_OE_DISABLE,	GATED_DQS,	INCLK_INPUT,	INPUT_ASYNC_RESET,	INPUT_POWER_UP,	INPUT_REGISTER_MODE,	INPUT_SYNC_RESET,	OE_ASYNC_RESET,	OE_POWER_UP,	OE_REGISTER_MODE,	OE_SYNC_RESET,	OPEN_DRAIN_OUTPUT,	OPERATION_MODE,	OUTPUT_ASYNC_RESET,	OUTPUT_POWER_UP,	OUTPUT_REGISTER_MODE,	OUTPUT_SYNC_RESET,	SIM_DQS_DELAY_INCREMENT,	SIM_DQS_INTRINSIC_DELAY,	SIM_DQS_OFFSET_INCREMENT,	TIE_OFF_OE_CLOCK_ENABLE,	TIE_OFF_OUTPUT_CLOCK_ENABLE) 
RETURNS ( combout, ddioregout, dqsbusout, linkout, padio, regout);

--synthesis_resources = stratixiigx_io 3 
SUBDESIGN ddio_out_t6f
( 
	datain_h[2..0]	:	input;
	datain_l[2..0]	:	input;
	dataout[2..0]	:	output;
	outclock	:	input;
) 
VARIABLE 
	ddio_outa[2..0] : stratixiigx_io
		WITH (
			DDIO_MODE = "output",
			OPERATION_MODE = "output",
			OUTPUT_ASYNC_RESET = "none",
			OUTPUT_POWER_UP = "low",
			OUTPUT_REGISTER_MODE = "register"
		);

BEGIN 
	ddio_outa[].datain = datain_h[];
	ddio_outa[].ddiodatain = datain_l[];
	ddio_outa[].outclk = outclock;
	dataout[] = ddio_outa[].padio;
END;
--VALID FILE