ddr2_v340_ecc.map.summary

基于SIIGX的PCIe的Kit

Analysis & Synthesis Status : Successful - Thu Aug 02 12:58:45 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : ddr2_v340_ecc
Top-level Entity Name : ddr2_v340_ecc
Family : Stratix II GX
Logic utilization : N/A
    Combinational ALUTs : 1,117
    Dedicated logic registers : 1,533
Total registers : 2136
Total pins : 140
Total virtual pins : 0
Total block memory bits : 2,592
DSP block 9-bit elements : 0
Total GXB Receiver Channels : 0
Total GXB Transmitter Channels : 0
Total PLLs : 1
Total DLLs : 1