ddr2_topecc_auk_ddr_dqs_group.v

基于SIIGX的PCIe的Kit

           \g_dq_io:0:dq_io .open_drain_output = "false",
           \g_dq_io:0:dq_io .operation_mode = "bidir",
           \g_dq_io:0:dq_io .output_async_reset = "clear",
           \g_dq_io:0:dq_io .output_power_up = "low",
           \g_dq_io:0:dq_io .output_register_mode = "register",
           \g_dq_io:0:dq_io .output_sync_reset = "none",
           \g_dq_io:0:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:0:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:0:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:0:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:0:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:1:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[1]),
      .ddiodatain (wdata_r[9]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[1]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[1]),
      .regout (dq_captured_falling[1]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:1:dq_io .bus_hold = "false",
           \g_dq_io:1:dq_io .ddio_mode = "bidir",
           \g_dq_io:1:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:1:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:1:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:1:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:1:dq_io .dqs_input_frequency = "none",
           \g_dq_io:1:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:1:dq_io .dqs_out_mode = "none",
           \g_dq_io:1:dq_io .dqs_phase_shift = 0,
           \g_dq_io:1:dq_io .extend_oe_disable = "false",
           \g_dq_io:1:dq_io .gated_dqs = "false",
           \g_dq_io:1:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:1:dq_io .input_async_reset = "clear",
           \g_dq_io:1:dq_io .input_power_up = "low",
           \g_dq_io:1:dq_io .input_register_mode = "register",
           \g_dq_io:1:dq_io .input_sync_reset = "none",
           \g_dq_io:1:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:1:dq_io .oe_async_reset = "clear",
           \g_dq_io:1:dq_io .oe_power_up = "low",
           \g_dq_io:1:dq_io .oe_register_mode = "register",
           \g_dq_io:1:dq_io .oe_sync_reset = "none",
           \g_dq_io:1:dq_io .open_drain_output = "false",
           \g_dq_io:1:dq_io .operation_mode = "bidir",
           \g_dq_io:1:dq_io .output_async_reset = "clear",
           \g_dq_io:1:dq_io .output_power_up = "low",
           \g_dq_io:1:dq_io .output_register_mode = "register",
           \g_dq_io:1:dq_io .output_sync_reset = "none",
           \g_dq_io:1:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:1:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:1:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:1:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:1:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:2:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[2]),
      .ddiodatain (wdata_r[10]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[2]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[2]),
      .regout (dq_captured_falling[2]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:2:dq_io .bus_hold = "false",
           \g_dq_io:2:dq_io .ddio_mode = "bidir",
           \g_dq_io:2:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:2:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:2:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:2:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:2:dq_io .dqs_input_frequency = "none",
           \g_dq_io:2:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:2:dq_io .dqs_out_mode = "none",
           \g_dq_io:2:dq_io .dqs_phase_shift = 0,
           \g_dq_io:2:dq_io .extend_oe_disable = "false",
           \g_dq_io:2:dq_io .gated_dqs = "false",
           \g_dq_io:2:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:2:dq_io .input_async_reset = "clear",
           \g_dq_io:2:dq_io .input_power_up = "low",
           \g_dq_io:2:dq_io .input_register_mode = "register",
           \g_dq_io:2:dq_io .input_sync_reset = "none",
           \g_dq_io:2:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:2:dq_io .oe_async_reset = "clear",
           \g_dq_io:2:dq_io .oe_power_up = "low",
           \g_dq_io:2:dq_io .oe_register_mode = "register",
           \g_dq_io:2:dq_io .oe_sync_reset = "none",
           \g_dq_io:2:dq_io .open_drain_output = "false",
           \g_dq_io:2:dq_io .operation_mode = "bidir",
           \g_dq_io:2:dq_io .output_async_reset = "clear",
           \g_dq_io:2:dq_io .output_power_up = "low",
           \g_dq_io:2:dq_io .output_register_mode = "register",
           \g_dq_io:2:dq_io .output_sync_reset = "none",
           \g_dq_io:2:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:2:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:2:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:2:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:2:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:3:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[3]),
      .ddiodatain (wdata_r[11]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[3]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[3]),
      .regout (dq_captured_falling[3]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:3:dq_io .bus_hold = "false",
           \g_dq_io:3:dq_io .ddio_mode = "bidir",
           \g_dq_io:3:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:3:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:3:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:3:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:3:dq_io .dqs_input_frequency = "none",
           \g_dq_io:3:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:3:dq_io .dqs_out_mode = "none",
           \g_dq_io:3:dq_io .dqs_phase_shift = 0,
           \g_dq_io:3:dq_io .extend_oe_disable = "false",
           \g_dq_io:3:dq_io .gated_dqs = "false",
           \g_dq_io:3:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:3:dq_io .input_async_reset = "clear",
           \g_dq_io:3:dq_io .input_power_up = "low",
           \g_dq_io:3:dq_io .input_register_mode = "register",
           \g_dq_io:3:dq_io .input_sync_reset = "none",
           \g_dq_io:3:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:3:dq_io .oe_async_reset = "clear",
           \g_dq_io:3:dq_io .oe_power_up = "low",
           \g_dq_io:3:dq_io .oe_register_mode = "register",
           \g_dq_io:3:dq_io .oe_sync_reset = "none",
           \g_dq_io:3:dq_io .open_drain_output = "false",
           \g_dq_io:3:dq_io .operation_mode = "bidir",
           \g_dq_io:3:dq_io .output_async_reset = "clear",
           \g_dq_io:3:dq_io .output_power_up = "low",
           \g_dq_io:3:dq_io .output_register_mode = "register",
           \g_dq_io:3:dq_io .output_sync_reset = "none",
           \g_dq_io:3:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:3:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:3:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:3:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:3:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:4:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[4]),
      .ddiodatain (wdata_r[12]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[4]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[4]),
      .regout (dq_captured_falling[4]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:4:dq_io .bus_hold = "false",
           \g_dq_io:4:dq_io .ddio_mode = "bidir",
           \g_dq_io:4:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:4:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:4:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:4:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:4:dq_io .dqs_input_frequency = "none",
           \g_dq_io:4:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:4:dq_io .dqs_out_mode = "none",
           \g_dq_io:4:dq_io .dqs_phase_shift = 0,
           \g_dq_io:4:dq_io .extend_oe_disable = "false",
           \g_dq_io:4:dq_io .gated_dqs = "false",
           \g_dq_io:4:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:4:dq_io .input_async_reset = "clear",
           \g_dq_io:4:dq_io .input_power_up = "low",
           \g_dq_io:4:dq_io .input_register_mode = "register",
           \g_dq_io:4:dq_io .input_sync_reset = "none",
           \g_dq_io:4:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:4:dq_io .oe_async_reset = "clear",
           \g_dq_io:4:dq_io .oe_power_up = "low",
           \g_dq_io:4:dq_io .oe_register_mode = "register",
           \g_dq_io:4:dq_io .oe_sync_reset = "none",
           \g_dq_io:4:dq_io .open_drain_output = "false",
           \g_dq_io:4:dq_io .operation_mode = "bidir",
           \g_dq_io:4:dq_io .output_async_reset = "clear",
           \g_dq_io:4:dq_io .output_power_up = "low",
           \g_dq_io:4:dq_io .output_register_mode = "register",
           \g_dq_io:4:dq_io .output_sync_reset = "none",
           \g_dq_io:4:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:4:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:4:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:4:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:4:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:5:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[5]),
      .ddiodatain (wdata_r[13]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[5]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[5]),
      .regout (dq_captured_falling[5]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:5:dq_io .bus_hold = "false",
           \g_dq_io:5:dq_io .ddio_mode = "bidir",
           \g_dq_io:5:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:5:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:5:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:5:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:5:dq_io .dqs_input_frequency = "none",
           \g_dq_io:5:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:5:dq_io .dqs_out_mode = "none",
           \g_dq_io:5:dq_io .dqs_phase_shift = 0,
           \g_dq_io:5:dq_io .extend_oe_disable = "false",
           \g_dq_io:5:dq_io .gated_dqs = "false",
           \g_dq_io:5:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:5:dq_io .input_async_reset = "clear",
           \g_dq_io:5:dq_io .input_power_up = "low",
           \g_dq_io:5:dq_io .input_register_mode = "register",
           \g_dq_io:5:dq_io .input_sync_reset = "none",
           \g_dq_io:5:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:5:dq_io .oe_async_reset = "clear",
           \g_dq_io:5:dq_io .oe_power_up = "low",
           \g_dq_io:5:dq_io .oe_register_mode = "register",
           \g_dq_io:5:dq_io .oe_sync_reset = "none",
           \g_dq_io:5:dq_io .open_drain_output = "false",
           \g_dq_io:5:dq_io .operation_mode = "bidir",
           \g_dq_io:5:dq_io .output_async_reset = "clear",
           \g_dq_io:5:dq_io .output_power_up = "low",
           \g_dq_io:5:dq_io .output_register_mode = "register",
           \g_dq_io:5:dq_io .output_sync_reset = "none",
           \g_dq_io:5:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:5:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:5:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:5:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:5:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:6:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[6]),
      .ddiodatain (wdata_r[14]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[6]),