ddr2_topecc_auk_ddr_dqs_group.v

基于SIIGX的PCIe的Kit

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// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

//------------------------------------------------------------------------------
//Parameters:
//Device Family                      : Stratix II
//DQ_PER_DQS                         : 8
//NON-DQS MODE                       : false
//use Resynch clock                  : true
//Resynch clock edge                 : rising
//Postamble Clock Edge               : falling
//Postamble Clock Cycle              : 4
//Intermediate Resynch               : true
//Intermediate Postamble             : false
//Pipeline read Data                 : true
//Enable Postamble Logic             : true
//Postamble Regs Per DQS             : 1
//Stratix Insert DQS delay buffers   : 0
//------------------------------------------------------------------------------
module ddr2_topecc_auk_ddr_dqs_group (
                                       // inputs:
                                        capture_clk,
                                        clk,
                                        control_be,
                                        control_doing_rd,
                                        control_doing_wr,
                                        control_dqs_burst,
                                        control_wdata,
                                        control_wdata_valid,
                                        dqs_delay_ctrl,
                                        dqsupdate,
                                        postamble_clk,
                                        reset_n,
                                        resynch_clk,
                                        write_clk,

                                       // outputs:
                                        control_rdata,
                                        ddr_dm,
                                        ddr_dq,
                                        ddr_dqs
                                     )
  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=C101;SUPPRESS_DA_RULE_INTERNAL=C105;SUPPRESS_DA_RULE_INTERNAL=C106;SUPPRESS_DA_RULE_INTERNAL=R104;SUPPRESS_DA_RULE_INTERNAL=A102;SUPPRESS_DA_RULE_INTERNAL=A103;SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=D101;SUPPRESS_DA_RULE_INTERNAL=D102;SUPPRESS_DA_RULE_INTERNAL=D103;SUPPRESS_DA_RULE_INTERNAL=R102;SUPPRESS_DA_RULE_INTERNAL=R105" */ ;

  parameter gSTRATIXII_DQS_OUT_MODE = "delay_chain3";
  parameter gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high";
  parameter gDLL_INPUT_FREQUENCY = "3000ps";
  parameter gSTRATIXII_DQS_PHASE = 9000;


  output  [ 15: 0] control_rdata;
  output           ddr_dm;
  inout   [  7: 0] ddr_dq;
  inout            ddr_dqs;
  input            capture_clk;
  input            clk;
  input   [  1: 0] control_be;
  input            control_doing_rd;
  input            control_doing_wr;
  input            control_dqs_burst;
  input   [ 15: 0] control_wdata;
  input            control_wdata_valid;
  input   [  5: 0] dqs_delay_ctrl;
  input            dqsupdate;
  input            postamble_clk;
  input            reset_n;
  input            resynch_clk;
  input            write_clk;

  wire             ZERO;
  wire    [  7: 0] ZEROS;
  wire    [ 13: 0] ZEROS_14;
  wire    [  1: 0] be;
  wire    [ 15: 0] control_rdata;
  wire             ddr_dm;
  wire    [  7: 0] ddr_dq;
  wire             ddr_dqs;
  wire    [ 15: 0] delayed_dq_captured;
  reg     [  1: 0] dm_out;
  wire             doing_rd;
  reg              doing_rd_delayed;
  reg     [  5: 0] doing_rd_pipe;
  wire             doing_wr;
  reg              doing_wr_r;
  wire             dq_capture_clk;
  wire    [ 15: 0] dq_captured_0;
  wire    [ 15: 0] dq_captured_1;
  wire    [ 15: 0] dq_captured_2;
  wire    [ 15: 0] dq_captured_3;
  wire    [ 15: 0] dq_captured_4;
  wire    [ 15: 0] dq_captured_5;
  wire    [  7: 0] dq_captured_falling;
  wire    [  7: 0] dq_captured_rising;
  reg     [  0: 0] dq_enable_reset;
  reg              dq_oe;
  wire             dqs_burst;
  wire    [  0: 0] dqs_clk;
  wire             dqs_oe;
  reg     [  0: 0] dqs_oe_r;
  reg     [ 15: 0] inter_rdata;
  wire    [  0: 0] not_dqs_clk;
  reg     [ 15: 0] rdata;
  wire             reset;
  reg     [ 15: 0] resynched_data;
  wire             tmp_dmout0;
  wire             tmp_dmout1;
  wire    [  0: 0] undelayed_dqs;
  wire    [ 15: 0] wdata;
  reg     [ 15: 0] wdata_r;
  wire             wdata_valid;
  //


  assign ZERO = 1'b0;
  assign ZEROS = 0;
  assign ZEROS_14 = 0;
  assign reset = ~reset_n;
  assign not_dqs_clk = ~dqs_clk;
  // rename user i/f signals, outputs
  assign control_rdata = rdata;

  // rename user i/f signals, inputs
  assign wdata = control_wdata;

  assign wdata_valid = control_wdata_valid;
  assign doing_wr = control_doing_wr;
  assign doing_rd = control_doing_rd;
  assign be = control_be;
  assign dqs_burst = control_dqs_burst;
  //-----------------------------------------------------------------------------
  //DQS pin and its logic
  //Generate the output enable for DQS from the signal that indicates we're
  //doing a write. The DQS burst signal is generated by the controller to keep
  //the DQS toggling for the required burst length.
  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
          dqs_oe_r <= 1'b0;
          doing_wr_r <= 1'b0;
        end
      else 
        begin
          dqs_oe_r <= dqs_oe;
          doing_wr_r <= doing_wr;
        end
    end


  assign dqs_oe = doing_wr | dqs_burst;
  //-----------------------------------------------------------------------------
  //DM pins and their logic
  //Although these don't get tristated like DQ, they do share the same IO timing.
  //-----------------------------------------------------------------------------
  assign tmp_dmout0 = dm_out[0];
  assign tmp_dmout1 = dm_out[1];
  altddio_out dm_pin
    (
      .aclr (reset),
      .aset (),
      .datain_h (tmp_dmout0),
      .datain_l (tmp_dmout1),
      .dataout (ddr_dm),
      .oe (1'b1),
      .outclock (write_clk),
      .outclocken (1'b1)
    );

  defparam dm_pin.extend_oe_disable = "UNUSED",
           dm_pin.intended_device_family = "Stratix II",
           dm_pin.invert_output = "OFF",
           dm_pin.lpm_hint = "UNUSED",
           dm_pin.lpm_type = "altddio_out",
           dm_pin.oe_reg = "UNUSED",
           dm_pin.power_up_high = "OFF",
           dm_pin.width = 1;

  //-----------------------------------------------------------------------------
  //Data mask registers
  //These are the last registers before the registers in the altddio_out. They
  //are clocked off the system clock but feed registers which are clocked off the
  //write clock, so their output is the beginning of 3/4 cycle path.
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dm_out <= {2{1'b1}};
      else if (doing_wr)
          // don't latch in data unless it's valid
          dm_out <= ~be;

      else 
        dm_out <= {2{1'b1}};
    end


  //-----------------------------------------------------------------------------
  //Logic to disable the capture registers (particularly during DQS postamble)
  //The output of the dq_enable_reset register holds the dq_enable register in
  //reset (which *enables* the dq capture registers). The controller releases
  //the dq_enable register so that it is clocked by the last falling edge of the
  //read dqs signal. This disables the dq capture registers during and after the
  //dqs postamble so that the output of the dq capture registers can be safely
  //resynchronised.
  //Postamble Clock Cycle  : 4
  //Postamble Clock Edge   : falling
  //Postamble Regs Per DQS : 1
  //-----------------------------------------------------------------------------

  //Use a falling edge for postamble
  //The registers which generate the reset signal to the above registers
  //Can be clocked off the resynch or system clock
  always @(negedge postamble_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dq_enable_reset <= 1'b0;
      else 
        dq_enable_reset <= doing_rd_delayed;
    end


  //pipeline the doing_rd signal to enable and disable the DQ capture regs at the right time
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          doing_rd_pipe <= 0;
      else 
        //shift bits up
        doing_rd_pipe <= {doing_rd_pipe[4 : 0], doing_rd};

    end


  //It's safe to clock from falling edge of clk to postamble_clk, so use falling edge clock
  always @(negedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          doing_rd_delayed <= 1'b0;
      else 
        doing_rd_delayed <= doing_rd_pipe[4];
    end


  //-----------------------------------------------------------------------------
  //Decide which clock to use for capturing the DQ data
  //-----------------------------------------------------------------------------
  //Use DQS to capture DQ read data
  assign dq_capture_clk = ~dqs_clk;

  //-----------------------------------------------------------------------------
  //DQ pins and their logic
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dq_oe <= 1'b0;
      else 
        dq_oe <= doing_wr;
    end


  stratixii_io \g_dq_io:0:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[0]),
      .ddiodatain (wdata_r[8]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[0]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[0]),
      .regout (dq_captured_falling[0]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:0:dq_io .bus_hold = "false",
           \g_dq_io:0:dq_io .ddio_mode = "bidir",
           \g_dq_io:0:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:0:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:0:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:0:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:0:dq_io .dqs_input_frequency = "none",
           \g_dq_io:0:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:0:dq_io .dqs_out_mode = "none",
           \g_dq_io:0:dq_io .dqs_phase_shift = 0,
           \g_dq_io:0:dq_io .extend_oe_disable = "false",
           \g_dq_io:0:dq_io .gated_dqs = "false",
           \g_dq_io:0:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:0:dq_io .input_async_reset = "clear",
           \g_dq_io:0:dq_io .input_power_up = "low",
           \g_dq_io:0:dq_io .input_register_mode = "register",
           \g_dq_io:0:dq_io .input_sync_reset = "none",
           \g_dq_io:0:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:0:dq_io .oe_async_reset = "clear",
           \g_dq_io:0:dq_io .oe_power_up = "low",
           \g_dq_io:0:dq_io .oe_register_mode = "register",
           \g_dq_io:0:dq_io .oe_sync_reset = "none",