ddr2_v340_ecc.fit.smsg

基于SIIGX的PCIe的Kit

    Info: Pin "ddr2_dq[68]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dq[69]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dq[70]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dq[71]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_dqs[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: group 1
        Info: Type bidirectional pin ddr2_dq[1] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[33] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[65] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[24] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[56] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[15] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[47] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[7] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[3] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[6] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[38] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[70] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[29] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[61] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[20] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[52] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[8] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[11] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[43] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[3] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[2] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[18] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[34] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[50] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[66] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[6] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[9] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[25] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[41] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[57] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[1] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[0] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[16] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[32] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[48] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[64] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[8] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[4] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[7] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[23] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[39] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[55] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[71] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[14] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[30] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[46] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[62] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[6] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[2] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[5] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[21] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[37] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[53] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[69] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[12] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[28] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[44] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[60] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[4] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[0] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[3] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[19] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[35] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[51] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[67] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[7] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[10] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[26] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[42] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[58] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[2] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[17] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[49] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[5] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[8] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[40] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[0] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[31] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[63] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[22] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[54] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[13] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[45] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dqs[5] uses the SSTL-18 Class II I/O standard
        Info: Type output pin ddr2_dm[1] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[4] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[36] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[68] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[27] uses the SSTL-18 Class II I/O standard
        Info: Type bidirectional pin ddr2_dq[59] uses the SSTL-18 Class II I/O standard
Info: Quartus II Fitter was successful. 0 errors, 8 warnings
    Info: Allocated 385 megabytes of memory during processing
    Info: Processing ended: Thu Aug 02 13:06:58 2007
    Info: Elapsed time: 00:08:07