ddr2_v340_ecc.fit.smsg

基于SIIGX的PCIe的Kit

    Info: Pin pnf_per_byte[11] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[12] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[13] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[14] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[15] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[16] not assigned to an exact location on the device
    Info: Pin pnf_per_byte[17] not assigned to an exact location on the device
Warning: Implemented PLL "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|pll" as Enhanced PLL type, but with warnings
    Warning: Can't achieve requested value 272.0 degrees for clock output ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk2 of parameter phase shift -- achieved value of 270.0 degrees
    Info: Implementing clock multiplication of 10, clock division of 3, and phase shift of 0 degrees (0 ps) for ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 10, clock division of 3, and phase shift of -90 degrees (-750 ps) for ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 port
    Info: Implementing clock multiplication of 10, clock division of 3, and phase shift of 270 degrees (2250 ps) for ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk2 port
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Automatically promoted node ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_6)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G5
Info: Automatically promoted node ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1 (placed in counter C2 of PLL_6)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
Info: Automatically promoted node ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk2 (placed in counter C1 of PLL_6)
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:03
    Extra Info: Packed 21 registers into blocks of type I/O
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 18 (unused VREF, 3.30 VCCIO, 0 input, 18 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  120 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  124 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  101 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  94 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 7 uses 0.90V VREF pins and has 1.80V VCCIO pins. 55 total pin(s) used --  39 pins available
        Info: I/O bank number 8 uses 0.90V VREF pins and has 1.80V VCCIO pins. 62 total pin(s) used --  38 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has 1.80V VCCIO pins. 6 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 13 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 14 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 15 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 16 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Starting physical synthesis optimizations
Info: Starting physical synthesis algorithm automatic asynchronous signal pipelining
Info: Automatic asynchronous signal pipelining - Evaluation Phase
    Info: Asynchronous signal |ddr2_v340_ecc|reset_n
        Info: Signal not critical. No action is required
    Info: Found 1 asynchronous signals of which 0 will be pipelined
Info: Physical synthesis algorithm automatic asynchronous signal pipelining complete
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 25 ps
Info: Starting physical synthesis algorithm combinational resynthesis 1
Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations complete: elapsed time is 00:01:02
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:01
    Extra Info: No registers were packed into other blocks
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "ddr2_a[13]" is assigned to location or region, but does not exist in design
    Warning: Node "ddr2_a[14]" is assigned to location or region, but does not exist in design
    Warning: Node "ddr2_ba[2]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:10
Info: Fitter placement operations beginning
Info: Starting physical synthesis optimizations
Info: Starting physical synthesis algorithm automatic asynchronous signal pipelining
Info: Automatic asynchronous signal pipelining - Execution Phase
Info: Physical synthesis algorithm automatic asynchronous signal pipelining complete
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 107 ps
Info: Starting physical synthesis algorithm combinational resynthesis 1
Info: Physical synthesis algorithm combinational resynthesis 1 complete: estimated slack improvement of 13 ps
Info: Starting physical synthesis algorithm logic and register replication
Info: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm combinational resynthesis 3
Info: Physical synthesis algorithm combinational resynthesis 3 complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations complete: elapsed time is 00:03:25
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:04:15
Info: Estimated most critical path is register to register delay of 3.392 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X48_Y3; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|dqs_burst_cas5'
    Info: 2: + IC(0.046 ns) + CELL(0.357 ns) = 0.403 ns; Loc. = LAB_X48_Y3; Fanout = 18; COMB Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_oe'
    Info: 3: + IC(2.711 ns) + CELL(0.278 ns) = 3.392 ns; Loc. = IOC_X86_Y0_N0; Fanout = 1; REG Node = 'ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_io~oe_reg'
    Info: Total cell delay = 0.635 ns ( 18.72 % )
    Info: Total interconnect delay = 2.757 ns ( 81.28 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 10%
    Info: The peak interconnect region extends from location X45_Y0 to location X55_Y10
Info: Fitter routing operations ending: elapsed time is 00:00:20
Info: Duplicated 1 combinational logic cells to improve design speed or routability
Info: Duplicated 3 registered logic cells to improve design speed or routability
Info: Started post-fitting delay annotation
Warning: Found 138 output pins without output pin load capacitance assignment
    Info: Pin "ddr2_a[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_a[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddr2_ba[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis