ddr2_v340_ecc.tan.summary

基于SIIGX的PCIe的Kit

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.213 ns
From           : reset_n
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5
From Clock     : --
To Clock       : clock_source
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.272 ns
From           : ddr2_topecc_example_driver:driver|compare_valid_reg[10]
To             : pnf_per_byte[10]
From Clock     : clock_source
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : 0.194 ns
Required Time  : 1.600 ns
Actual Time    : 1.406 ns
From           : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|dq_captured_falling[0]
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|resynched_data[8]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.974 ns
From           : reset_n
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|time_writes_cas5
From Clock     : --
To Clock       : clock_source
Failed Paths   : 0

Type           : Worst-case Maximum Data Arrival Skew
Slack          : 0.090 ns
Required Time  : 0.100 ns
Actual Time    : 0.010 ns
From           : clk_to_sdram_p[0]
To             : clk_to_sdram_n[0]
From Clock     : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
Slack          : -0.420 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : 292.40 MHz ( period = 3.420 ns )
From           : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|local_rdata_valid
To             : ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst|lfsr_data[0]
From Clock     : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
Failed Paths   : 77

Type           : Clock Setup: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
Slack          : 0.381 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|wdata_r[7]
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|\g_dq_io:7:dq_io~data_in_reg
From Clock     : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
Slack          : 0.018 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|trfc_pipe[23]
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|trfc_pipe[24]
From Clock     : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
Slack          : 1.105 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|doing_rd_delayed
To             : ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|dq_enable_reset[0]
From Clock     : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 77

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