ddr2_v340_ecc.qsf

基于SIIGX的PCIe的Kit

set_location_assignment LAB_X13_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[1]"
set_location_assignment LAB_X13_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[9]"
set_location_assignment PIN_AR28 -to ddr2_dq[58]
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[2]"
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[10]"
set_location_assignment PIN_AT29 -to ddr2_dq[59]
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[3]"
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[11]"
set_location_assignment PIN_AU30 -to ddr2_dq[60]
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[4]"
set_location_assignment LAB_X15_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[12]"
set_location_assignment PIN_AW30 -to ddr2_dq[61]
set_location_assignment LAB_X16_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[5]"
set_location_assignment LAB_X16_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[13]"
set_location_assignment PIN_AW31 -to ddr2_dq[62]
set_location_assignment LAB_X17_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[6]"
set_location_assignment LAB_X17_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[14]"
set_location_assignment PIN_AU31 -to ddr2_dq[63]
set_location_assignment LAB_X17_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[7]"
set_location_assignment LAB_X17_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:7:g_ddr_io|resynched_data[15]"
set_location_assignment PIN_AU28 -to ddr2_dqs[7]
set_location_assignment PIN_AV30 -to ddr2_dm[7]
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "NEVER ALLOW" -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io"
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io"
set_location_assignment PIN_AW32 -to ddr2_dq[64]
set_location_assignment LAB_X7_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[0]"
set_location_assignment LAB_X7_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[8]"
set_location_assignment LAB_X7_Y2 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|dq_enable_reset[0]"
set_location_assignment PIN_AU32 -to ddr2_dq[65]
set_location_assignment LAB_X7_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[1]"
set_location_assignment LAB_X7_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[9]"
set_location_assignment PIN_AU33 -to ddr2_dq[66]
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[2]"
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[10]"
set_location_assignment PIN_AW34 -to ddr2_dq[67]
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[3]"
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[11]"
set_location_assignment PIN_AW35 -to ddr2_dq[68]
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[4]"
set_location_assignment LAB_X9_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[12]"
set_location_assignment PIN_AV34 -to ddr2_dq[69]
set_location_assignment LAB_X10_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[5]"
set_location_assignment LAB_X10_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[13]"
set_location_assignment PIN_AV37 -to ddr2_dq[70]
set_location_assignment LAB_X11_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[6]"
set_location_assignment LAB_X11_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[14]"
set_location_assignment PIN_AW37 -to ddr2_dq[71]
set_location_assignment LAB_X11_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[7]"
set_location_assignment LAB_X11_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:8:g_ddr_io|resynched_data[15]"
set_location_assignment PIN_AW33 -to ddr2_dqs[8]
set_location_assignment PIN_AW36 -to ddr2_dm[8]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_location_assignment PIN_AW22 -to clock_source
set_instance_assignment -name IO_STANDARD "1.8 V" -to test_complete
set_location_assignment PIN_AR33 -to test_complete
set_instance_assignment -name IO_STANDARD "1.8 V" -to pnf
set_location_assignment PIN_AP30 -to pnf
set_instance_assignment -name IO_STANDARD "1.8 V" -to heartbeat
set_location_assignment PIN_AT31 -to heartbeat
set_instance_assignment -name IO_STANDARD "1.8 V" -to reset_n
set_location_assignment PIN_AM22 -to reset_n
set_location_assignment PIN_AP16 -to ddr2_a[0]
set_location_assignment PIN_AH28 -to ddr2_a[1]
set_location_assignment PIN_AP26 -to ddr2_a[2]
set_location_assignment PIN_AP29 -to ddr2_a[3]
set_location_assignment PIN_AL15 -to ddr2_a[4]
set_location_assignment PIN_AK27 -to ddr2_a[5]
set_location_assignment PIN_AK25 -to ddr2_a[6]
set_location_assignment PIN_AU29 -to ddr2_a[7]
set_location_assignment PIN_AH15 -to ddr2_a[8]
set_location_assignment PIN_AH25 -to ddr2_a[9]
set_location_assignment PIN_AT30 -to ddr2_a[10]
set_location_assignment PIN_AN21 -to ddr2_a[11]
set_location_assignment PIN_AP28 -to ddr2_a[12]
set_location_assignment PIN_AL28 -to ddr2_a[13]
set_location_assignment PIN_AG19 -to ddr2_a[14]
set_location_assignment PIN_AN28 -to ddr2_ba[0]
set_location_assignment PIN_AG24 -to ddr2_ba[1]
set_location_assignment PIN_AH27 -to ddr2_ba[2]
set_location_assignment PIN_AJ27 -to ddr2_ras_n
set_location_assignment PIN_AG23 -to ddr2_cas_n
set_location_assignment PIN_AL13 -to ddr2_we_n
set_location_assignment PIN_AF18 -to ddr2_cke
set_location_assignment PIN_AJ25 -to ddr2_cs_n
set_location_assignment PIN_AN25 -to ddr2_odt
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SEED 1
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_tb_functions.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_avalon_if.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd"
set_global_assignment -name VHDL_FILE "altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd"
set_global_assignment -name VERILOG_FILE ddr2_topecc.v