📄 ddr2_v340_ecc.map.rpt
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; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+--------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+
; altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd ; yes ; Encrypted User VHDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_functions.vhd ;
; altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd ; yes ; Encrypted User VHDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_input_buf.vhd ;
; altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd ; yes ; Encrypted User VHDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_timers.vhd ;
; altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd ; yes ; Encrypted User VHDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_bank_details.vhd ;
; altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd ; yes ; Encrypted User VHDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr2_init.vhd ;
; ddr2_topecc.v ; yes ; User Verilog HDL File ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc.v ;
; ddr2_v340_ecc.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_v340_ecc.v ;
; ddr2_topecc_auk_ddr_sdram.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_sdram.v ;
; auk_ddr_controller.vhd ; yes ; Encrypted File ; E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/auk_ddr_controller.vhd ;
; scfifo.tdf ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal70.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/aglobal70.inc ;
; db/scfifo_e691.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/scfifo_e691.tdf ;
; db/a_dpfifo_7u11.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/a_dpfifo_7u11.tdf ;
; db/altsyncram_a6e1.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/altsyncram_a6e1.tdf ;
; db/cntr_bu8.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/cntr_bu8.tdf ;
; db/cntr_qs7.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/cntr_qs7.tdf ;
; db/cntr_cu8.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/cntr_cu8.tdf ;
; ddr2_topecc_auk_ddr_datapath.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_datapath.v ;
; ddr2_topecc_auk_ddr_clk_gen.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_clk_gen.v ;
; altddio_out.tdf ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/altddio_out.tdf ;
; mercury_ddio.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/mercury_ddio.inc ;
; apexii_ddio.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/apexii_ddio.inc ;
; stratix_ddio.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/stratix_ddio.inc ;
; cyclone_ddio.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/cyclone_ddio.inc ;
; lpm_mux.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/lpm_mux.inc ;
; stratix_lcell.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/stratix_lcell.inc ;
; db/ddio_out_t6f.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/ddio_out_t6f.tdf ;
; ddr2_topecc_auk_ddr_dqs_group.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dqs_group.v ;
; db/ddio_out_tkf.tdf ; yes ; Auto-Generated Megafunction ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/db/ddio_out_tkf.tdf ;
; ddr2_topecc_example_driver.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_example_driver.v ;
; example_lfsr8.v ; yes ; Other ; E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/altera/MegaCore/ddr_ddr2_sdram-v3.4.0/lib/example_lfsr8.v ;
; ddr_pll_stratixii.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr_pll_stratixii.v ;
; altpll.tdf ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/altpll.tdf ;
; stratix_pll.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/altera/70/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; ddr2_topecc_auk_ddr_dll.v ; yes ; Other ; F:/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/ddr2_v340_ecc_restored/ddr2_topecc_auk_ddr_dll.v ;
+--------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------------------+---------------------------------------------------------------------------+
; Resource ; Usage ;
+-----------------------------------------------+---------------------------------------------------------------------------+
; Estimated ALUTs Used ; 1117 ;
; Dedicated logic registers ; 1533 ;
; ; ;
; Estimated ALUTs Unavailable ; 195 ;
; ; ;
; Total combinational functions ; 1117 ;
; Combinational ALUT usage by number of inputs ; ;
; -- 7 input functions ; 2 ;
; -- 6 input functions ; 169 ;
; -- 5 input functions ; 150 ;
; -- 4 input functions ; 240 ;
; -- <=3 input functions ; 556 ;
; ; ;
; Combinational ALUTs by mode ; ;
; -- normal mode ; 980 ;
; -- extended LUT mode ; 2 ;
; -- arithmetic mode ; 135 ;
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