ddr2_v340_ecc.map.rpt

基于SIIGX的PCIe的Kit

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; Analysis & Synthesis Settings                                                                      ;
+----------------------------------------------------------+--------------------+--------------------+
; Option                                                   ; Setting            ; Default Value      ;
+----------------------------------------------------------+--------------------+--------------------+
; Device                                                   ; EP2SGX90FF1508C3   ;                    ;
; Top-level entity name                                    ; ddr2_v340_ecc      ; ddr2_v340_ecc      ;
; Family name                                              ; Stratix II GX      ; Stratix            ;
; Optimization Technique -- Stratix II/Stratix III         ; Speed              ; Balanced           ;
; Restructure Multiplexers                                 ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                      ; Off                ; Off                ;
; Preserve fewer node names                                ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                ; Off                ; Off                ;
; Verilog Version                                          ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                             ; VHDL93             ; VHDL93             ;
; State Machine Processing                                 ; Auto               ; Auto               ;
; Safe State Machine                                       ; Off                ; Off                ;
; Extract Verilog State Machines                           ; On                 ; On                 ;
; Extract VHDL State Machines                              ; On                 ; On                 ;
; Ignore Verilog initial constructs                        ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                  ; On                 ; On                 ;
; DSP Block Balancing                                      ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                  ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                       ; On                 ; On                 ;
; Power-Up Don't Care                                      ; On                 ; On                 ;
; Remove Redundant Logic Cells                             ; Off                ; Off                ;
; Remove Duplicate Registers                               ; On                 ; On                 ;
; Ignore CARRY Buffers                                     ; Off                ; Off                ;
; Ignore CASCADE Buffers                                   ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                ; Off                ; Off                ;
; Ignore LCELL Buffers                                     ; Off                ; Off                ;
; Ignore SOFT Buffers                                      ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                           ; Off                ; Off                ;
; Carry Chain Length -- Stratix II/Stratix III             ; 70                 ; 70                 ;
; Auto Carry Chains                                        ; On                 ; On                 ;
; Auto Open-Drain Pins                                     ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                    ; Off                ; Off                ;
; Perform gate-level register retiming                     ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax   ; On                 ; On                 ;
; Auto ROM Replacement                                     ; On                 ; On                 ;
; Auto RAM Replacement                                     ; On                 ; On                 ;
; Auto DSP Block Replacement                               ; On                 ; On                 ;
; Auto Shift Register Replacement                          ; On                 ; On                 ;
; Auto Clock Enable Replacement                            ; On                 ; On                 ;
; Allow Synchronous Control Signals                        ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                   ; Off                ; Off                ;
; Auto RAM Block Balancing                                 ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                        ; Off                ; Off                ;
; Auto Resource Sharing                                    ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                       ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                       ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition            ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                     ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K/M9K Memory Blocks                  ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM/M144K Memory Blocks              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and synthesis_off directives        ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report       ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                       ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length         ; 2                  ; 2                  ;
; PowerPlay Power Optimization                             ; Normal compilation ; Normal compilation ;
; HDL message level                                        ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages          ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report ; 100                ; 100                ;
; Use smart compilation                                    ; Off                ; Off                ;
+----------------------------------------------------------+--------------------+--------------------+


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