📄 ddr2_v340_ecc.map.rpt
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64. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io
65. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io|altddio_out:dm_pin
66. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io
67. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|altddio_out:dm_pin
68. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io
69. Parameter Settings for User Entity Instance: ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io|altddio_out:dm_pin
70. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_0_lfsr_inst
71. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_1_lfsr_inst
72. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_2_lfsr_inst
73. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_3_lfsr_inst
74. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_4_lfsr_inst
75. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_5_lfsr_inst
76. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_6_lfsr_inst
77. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_7_lfsr_inst
78. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_8_lfsr_inst
79. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_9_lfsr_inst
80. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_10_lfsr_inst
81. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_11_lfsr_inst
82. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_12_lfsr_inst
83. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_13_lfsr_inst
84. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_14_lfsr_inst
85. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_15_lfsr_inst
86. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_16_lfsr_inst
87. Parameter Settings for User Entity Instance: ddr2_topecc_example_driver:driver|example_lfsr8:LFSRGEN_17_lfsr_inst
88. Parameter Settings for User Entity Instance: ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component
89. scfifo Parameter Settings by Entity Instance
90. Analysis & Synthesis INI Usage
91. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+--------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Aug 02 12:58:45 2007 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; ddr2_v340_ecc ;
; Top-level Entity Name ; ddr2_v340_ecc ;
; Family ; Stratix II GX ;
; Logic utilization ; N/A ;
; Combinational ALUTs ; 1,117 ;
; Dedicated logic registers ; 1,533 ;
; Total registers ; 2136 ;
; Total pins ; 140 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 2,592 ;
; DSP block 9-bit elements ; 0 ;
; Total GXB Receiver Channels ; 0 ;
; Total GXB Transmitter Channels ; 0 ;
; Total PLLs ; 1 ;
; Total DLLs ; 1 ;
+--------------------------------+-----------------------------------------+
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